Sign-in / Sign-up
Your question

Microarchitecture brief

Tags:
  • CPUs
  • Performance
Last response: in CPUs
March 10, 2006 5:31:53 AM

Instead of bickering over theoretical performance benchmarks, if you want to learn something about why the new cores are faster view the flash demo at this URL:

http://www.intel.com/technology/architecture/coremicro/

The technical briefs are extremely well done and the flash demo is great for people who don't understand all the technical terms of processor microarchitecture. There's more to the design than integrated memory controllers, DDR vs. DDR2, FSB speeds, etc.

Understand that these concepts of microprocessors apply to all AMD and Intel CPUs, each family simply has their own implementation.

Personally I am very excited about the potential performance boost in SSE3 applications. Previously the main advantage to SSE3, speed wise, were the caching instructions which helped with preloading massive amounts of data for just-in-time execution. The instructions themselves did not execute any faster.

But, you know, come to think of it... I don't think I know of any applications that use SSE3. :( 

Anyone know of a good link to an indepth description of K8 architecture? I couldn't find anything good on AMD's site. I don't think they wanted Intel to find out what was in their secret sauce. :wink:

More about : microarchitecture

March 10, 2006 5:37:26 AM

I believe premiere uses SSE3. I also though the instruction caching thing was SSE2?

For the K8 i like Sandpile. Great for stats. Hannibals write up on the K8 was also pretty solid.
Related resources
March 10, 2006 3:38:40 PM

Ah I was wrong about the cachability being in SSE3. It actually originated in the first SSE instruction set.

SSE3 added some more advanced math instructions and threading synchronization instructions, which I think is very handy in multicore CPUs.

Thanks for the sandpile link. Very helpful.
March 10, 2006 4:39:23 PM

Excellent post! I'm glad someone out there is trying to show what Intel really did to get back into the performance game.

Alot of people just don't understand the processor architecture overhaul that they did.
Anonymous
a b à CPUs
March 10, 2006 5:04:20 PM

Quote:
Ah I was wrong about the cachability being in SSE3. It actually originated in the first SSE instruction set.

SSE3 added some more advanced math instructions and threading synchronization instructions, which I think is very handy in multicore CPUs.

Thanks for the sandpile link. Very helpful.


I beleive the SS3 threading synchronization instructions where mainly for hyperthread but I could be wrong anyone?
March 11, 2006 3:26:51 AM

Considering the instructions are implemented on the application side and they are also valid in AMD processors which do not support HT, I doubt it.

HT is a hardware change and is software transparent.