http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears...
The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.
[/quote]These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect (hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.[/quote]
The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.
[/quote]These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect (hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.[/quote]