Sign in with
Sign up | Sign in
Your question

AMD SAYS IT CAN STILL BEAT INTEL CORES WITH OPTERONS

Last response: in CPUs
Share
March 16, 2006 11:25:46 PM

http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

[/quote]These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect (hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.[/quote]
March 16, 2006 11:27:30 PM

If only they could get you a new keyboard.
March 16, 2006 11:50:33 PM

Well.. new keyboard MINUS a cap lock/shift button. :lol: 
Related resources
March 17, 2006 12:43:58 AM

hmm... a keyboard with a comma key on the keypad would be nice :lol: 
March 17, 2006 1:14:44 AM

Quote:
http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

Quote:
These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect
Quote:
(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.


Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time
March 17, 2006 1:17:45 AM

Quote:
http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect (hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.



AWESOME :-D

I'll take 2 please.
March 17, 2006 2:06:16 AM

Quote:


.. With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.


Exactly which server makers are you referring to ?, as all the ones I've seen since 2003 have been offering 4 and 8 socket boards.
- HP / Compaq, Sun Microsystems, Iwill, Tyan, SuperMicro, and many others all are, and have been for ages.

Bear in mind the boards alone will cost US$500 - US$1000, just like they do now, and likely incorperate Serial Attached SCSI (SAS) supporting more than a home user will ever need.

As AMD use ccNUMA via HyperTransport they scaled ****ing well, far better than Xeons do past 4 processor cores. (The scaling was almost linear, and you can't get better than linear scaling).

The cache latency, from socket to socket (the worst cache scenario), due to the above (ccNUMA), was actually one of the lowest on the market.... well under 100 nanoseconds.

I can't figure out why the AMD fanboys here don't read the AMD websites:
http://multicore.amd.com - In particular has been running for ages, and explains it all fairly well.

Windows XP Pro, and Windows XP Pro x64 Edition, both support NUMA out of the box without modification btw.

If they implement L3 cache structure it'll either be:
- L3 cache per CPU socket
- L2 cache per CPU core

or something more along the lines of the L2/L3 layout some Sun UltraSPARC servers use:
- http://www.sun.com/servers/index.jsp
- Lots of reading on the Sun website regarding some rather smart 'cache structures' as you put it.
- If I recall correctly you want to 'compare' it to the 'boards' that the UltraSPARC IV / IV+ are being installed on for a 'rough' idea of how AMD might do it to get even better scalability than now.

However with 2 x boards, each with 4 x sockets, and 4 x cores per socket they'll get to 32 cores easily..... and most Operating Systems don't support more than 32 'processors'. So you want each of said processor (/core/SMT/CMT/HT/whatever/etc) to be giving the best damn performance it can give.

The problem is the interconnect between the '2 x boards', as all the processors on the same board can aggregate memory throughput to the sky. I mean an aggregate 25.6 GB/sec (moving to 51.2 GB, then over 96 GB/sec later on) basically 'is' a level 3 cache, but not when a CPU on board A tries to share / access memory that a CPU on board B is in control of. (Requires more expensive / advanced chipset than what I am using now :p )

eg: The Opteron 800 series can aggregate its own memory from its own memory controller and basically treat 3 other processors as 'northbridges' to the memory they are controlling. Using NUMA (WinXP, Linux, etc all support it) you can start hitting 20 GB/sec (on small reads including latency), and can sustain closer to 24+ GB/sec when streaming or performing reads of 128 bytes or more.

See: http://users.on.net/~darkpeace/forum_images/hit-a-brick... ; for a rough idea. (EDIT: Well... that was actually the CPU performance test in SANDRA, not memory after all.... but it kicked his systems ass :p  - If anyone asks me, via PM, I'll run some more tests and post the results... otherwise I'll assume people have no real interest in the subject).

That image is of my own SANDRA results with the TomsHardware forums in the background on the very thread that asked for them, because someone didn't believe me. :p 

==================================

Also have a look at the http://www.tyan.com website, the Opteron section in particular of course.

We've got HyperText and can link to public documents almost anywhere in the world, might aswell use it.
a b à CPUs
March 17, 2006 2:09:30 AM

Quote:
http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

Quote:
These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect
Quote:
(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.


Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Woodcrest comes in at 2.93ghz, FBDIM and DIB will push it faster then the opterons for atleast 4 to 8way (a 2.66 can take on a A64, whats 2.93 going to do).

When intel gives us this type of hype we complain, but when were talkin AMD we dont - total BS - its just hype.

Besides - when Intel moves into the whole IMC and CSI (if there still usin csi) it will boost like the move to the K7->K8.
a b à CPUs
March 17, 2006 2:12:23 AM

Quote:
http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

Quote:
These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect
Quote:
(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.


Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Oooo!! not to be a fanboy buy didnt you say that bout AMD desktop cpus?
March 17, 2006 2:17:30 AM

Quote:
http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

Quote:
These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect
Quote:
(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.


Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Woodcrest comes in at 2.93ghz, FBDIM and DIB will push it faster then the opterons for atleast 4 to 8way (a 2.66 can take on a A64, whats 2.93 going to do).

When intel gives us this type of hype we complain, but when were talkin AMD we dont - total BS - its just hype.

Besides - when Intel moves into the whole IMC and CSI (if there still usin csi) it will boost like the move to the K7->K8.


Any statements coming from Intel are gospell and statements from AMD are BS, we all know that right?
March 17, 2006 2:17:45 AM

Quote:
http://www.itjungle.com/breaking/bn031506-story01.htmlMusic to my ears... :wink:

The best thing of K8L is that it will not use HTT 2.0, instead, they'll jump straight to HTT 3.0. That's fantastic since this can scale MP systems up to 32 way.

Quote:
These Rev G chips make jump from HyperTransport 1.0 to the HyperTransport 3.0 interconnect
Quote:
(hey, what happened to HyperTransport 2.0?), and a new architecture that incorporates L3 cache. (The rumor is that it will be a few megabytes of cache, and it will be on the die, not in the package alongside the die.) With the initial Opterons and the Thor chipset from AMD, the cache structure allowed server makers to gluelessly create servers with two, four, six, or eight sockets, and strangely enough, very few of them have. (The cache memory latencies apparently were very high, so the SMP scalability you got was not that great.) With the next generation of Opterons due in 2007, the L2/L3 cache architecture will also glueless connection of up to 32 cores--and maybe even more--without extra chipset work.


Not to be a fanboy, but the Opteron 64 will always be the dominate server chip. Period.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Woodcrest comes in at 2.93ghz, FBDIM and DIB will push it faster then the opterons for atleast 4 to 8way (a 2.66 can take on a A64, whats 2.93 going to do).

When intel gives us this type of hype we complain, but when were talkin AMD we dont - total BS - its just hype.

Besides - when Intel moves into the whole IMC and CSI (if there still usin csi) it will boost like the move to the K7->K8.

Whatever you say Apache... :roll:

~~Mad Mod Mike, pimpin' the world 1 rig at a time
March 17, 2006 2:56:52 AM

MadModMike, don't stand too proud, Conroe is gonna smack you in your face. It will humble you :oops: 
March 17, 2006 3:00:27 AM

Quote:
It would be very interesting to see AMD make dual-core chips using the same 65 nanometer process, and get the power use way down below 50 watts. Some customers want the same performance and less heat, and still other customers will take even less performance for a lot less heat.


mmm now that would be lovely...


Quote:
Intel's initial quad-core Xeon chips will actually be two dual-core chips sharing the same package (as it did to make the dual-core "Paxville" Xeons from single core "Irwindale" Xeons to blunt, however ineffectively, AMD's actual dual-core Opterons), but AMD will be doing real quad-core chips, putting four cores, probably with a per-core L2 cache and a shared L3 cache, on a single die.



Sorry, Intel fans... but which sounds like the better tech? Not that I'm a fan boy or anything. :roll:
March 17, 2006 3:13:39 AM

Quote:
MadModMike, don't stand too proud, Conroe is gonna smack you in your face. It will humble you :oops: 


lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.

~~Mad Mod Mike, pimpin' the world 1 rig at a time
March 17, 2006 3:36:50 AM

I would wait for the final release before you get too crazy. Have you forgot about the 4ghz P4 that was shown in 2003? I'm not saying Conroe won't be a good chip but wait until you have a mass produced chip to test, then you will know what you really have.
March 17, 2006 3:45:36 AM

Quote:
I would wait for the final release before you get too crazy. Have you forgot about the 4ghz P4 that was shown in 2003? I'm not saying Conroe won't be a good chip but wait until you have a mass produced chip to test, then you will know what you really have.


:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.
March 17, 2006 5:13:38 AM

AMD probably will do better when going past 4 cpus because of hypertransport. intel will have to integrate the memory controller to compete that way.


Quote:

lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.


you've read all the reviews and reports that say AM2 is about 3 - 5% faster than s939, right?


Quote:
:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.


you're giving AMD too much credit. 3+ years old? like AMD hasn't made revisions and enhancements to their manufacturing process.

besides, you won't see big performance gains like the p4 did when they switch to 65nm. the p4 benefitted because of it's architecture. look at the pentium m, it didn't have any problems on 90nm, unlike the p4. AMD will be able to scale clocks higher and reduce heat, doubt performance will shoot through the roof.
a b à CPUs
March 17, 2006 5:41:54 AM

Quote:
AMD probably will do better when going past 4 cpus because of hypertransport. intel will have to integrate the memory controller to compete that way.



lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.


you've read all the reviews and reports that say AM2 is about 3 - 5% faster than s939, right?


Quote:
:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.


you're giving AMD too much credit. 3+ years old? like AMD hasn't made revisions and enhancements to their manufacturing process.

besides, you won't see big performance gains like the p4 did when they switch to 65nm. the p4 benefitted because of it's architecture. look at the pentium m, it didn't have any problems on 90nm, unlike the p4. AMD will be able to scale clocks higher and reduce heat, doubt performance will shoot through the roof.

DIB made a dual socket P4 perform faster then the opterons at the time - intel 8 way and below will be quicker, the FSB isnt as slow as we expected - P4 was FSB hungry cause of its design, conroe etc isnt, and besides - who buys 16way servers - majority of the market isnt and when there going that high end they may as well go a diffrent brand chip for the purpose depending on needs ofcourse.

AMD 65nm THIS year? really?

Quote:
Any statements coming from Intel are gospell and statements from AMD are BS, we all know that right?
- nope but AMD is BSing like intel does but no one complains bout AMDs BS.

And whats wrong with two dual core dies on one package? we've seen it on 65nm pentium d's - its a better idea then all in one package, also just cause AMD DOESNT USE IT - wait till they do. Its a great idea to get more high speeds.

If AMD does do quad core and with 90nm they will have a choice - slow warm chips, or slightly faster and hot chips - 90nm is at an end for them.
March 17, 2006 10:29:01 AM

AMD tries to tell us a lot of things >_>
March 17, 2006 10:42:58 AM

No they aren't. AMD has shown the road maps and they'll arrive no sooner than 2007.
Opteron is the only contestor from the AMD side that i think will stay strong. The other's will get ripped apart(if they haven't already like the Poorion).
March 17, 2006 12:13:25 PM

Quote:
AMD tries to tell us a lot of things >_>


and Intel completely lives up to all their hype everytime. :roll:

lol. :twisted:
March 17, 2006 12:15:49 PM

Quote:
AMD probably will do better when going past 4 cpus because of hypertransport. intel will have to integrate the memory controller to compete that way.



lol how is a piece of silicon gonna do anything but be my personal space heater? I'm sure Conroe is gonna smack me in the face...so I'll turn the other cheek and let AM2 smack Conroe 8O.


you've read all the reviews and reports that say AM2 is about 3 - 5% faster than s939, right?


Quote:
:trophy: :trophy:

Indeed it is important to wait and see what happens.

Besides 65nm AMD CPUs are expected this year.

Trying to compare a 65nm Intel part against a 3+ year old 90nm part is INSANE.


you're giving AMD too much credit. 3+ years old? like AMD hasn't made revisions and enhancements to their manufacturing process.

besides, you won't see big performance gains like the p4 did when they switch to 65nm. the p4 benefitted because of it's architecture. look at the pentium m, it didn't have any problems on 90nm, unlike the p4. AMD will be able to scale clocks higher and reduce heat, doubt performance will shoot through the roof.


The architecture is over 3 years old.

The performance gains Intel claims for their 65nm line are not impressive at all considering. If this is the best they can do they will be in trouble.
March 17, 2006 12:24:08 PM

And the point is?

And yes, with Conroe they will live up to the hype.
March 17, 2006 12:27:39 PM

Quote:
And the point is?

And yes, with Conroe they will live up to the hype.



How do you know?

Do you have proof?

Manufacturers make claims all the time and rarely live up to them.

What is so special about the Conroe?

How much is Intel paying you???????????????
March 17, 2006 1:35:05 PM

About Conroe
Well there are benchies, and other builds using similar technology that curently rock hard. No matter how you take it Conroe will beat AM2 clock per clock. By how much,well i predict somewhere around 15% .
About AM2
We do have a THG benchmark that is of course coursed with the mem. controller bug(or so you insist) but we also have a Inq. article stating that AM2 with DDR2 800 will bring a minor 3-5% improvement over AMD on 939 with DDR that certainly can be placed as a fact.

AM2 will launch 2 months earlier than Conroe.

Not to mention that the Conroe hype is also infecting AMD people. They have finally admited that they'll have some nasty competition.

BTW Poorion X2 will be on the shelves soon. I can't wait to see how poo or not poo it performs.
March 17, 2006 2:08:30 PM

Quote:
About Conroe
Well there are benchies, and other builds using similar technology that curently rock hard. No matter how you take it Conroe will beat AM2 clock per clock. By how much,well i predict somewhere around 15% .
About AM2
We do have a THG benchmark that is of course coursed with the mem. controller bug(or so you insist) but we also have a Inq. article stating that AM2 with DDR2 800 will bring a minor 3-5% improvement over AMD on 939 with DDR that certainly can be placed as a fact.

AM2 will launch 2 months earlier than Conroe.

Not to mention that the Conroe hype is also infecting AMD people. They have finally admited that they'll have some nasty competition.

BTW Poorion X2 will be on the shelves soon. I can't wait to see how poo or not poo it performs.


CompGeek has a very level head about this and makes these very valid points:

- Conroe will have significant gains, probably not as much as Intel says, but still enough to best any of AMD's products
- AM2 is a step in the right direction, but is only a minor improvement
- The competition will be very, very nasty. Which is great for us!
March 17, 2006 2:16:54 PM

wel, in my humble opinion Intel did AMD (and its own fanbois) a big favor previewing Conroe at such an early stage.

AMD now has loads of time to prepare for it if they underestimated it.

this should be very interesting as judging by the way AMD are being quiet, last time the hammer was released (when everybody was talking and fanbois dreaming of Northwood>>>Axp) which showed some good advances.

Now that Intel is doing the preview this manner I expect also AMD to release their ace at the same time frame. (If not I guess amd sucks :p )

anyway, I seriously doubt that Conroe will stand alone as leader of performance for long on the desktop.

oon the laptop Turion X2 will be much more refined (Xbit) and more then likely in Intel's Core duo league, and on the server area I heard (inq) there's a floating point monster waiting for woodcrest's release.

anyway, glad that we're going to see some good improvements from both at the end of the year.
March 17, 2006 2:49:53 PM

Yup It'll be quite a clash. And of course it will benefit the costumers.
I'm already in the process of getting some of my future rig components. I'll skip of course the mobo and CPU since i'm not in a very big hurry.
My main concern with Conroe is that the posted prices may very well rise if it proves to be good. With AM2 the availability of DDR2 800mhz bugs me,in fact that goes for both.
DDR2 is a step in the right direction. It may not bring much but DDR is already showing strains. DDR2 should give some breathing space.
A year full of surprises(mostly nice i say) is expected.
March 17, 2006 3:01:17 PM

I think we should also keep in mind that the Pentium 4 is a real piece of junk: no wonder Conroe is considered a "leap forward".
AMD may not be able to improve as much as Intel did cause its starting point is an architecture which is already valid.

This said, IF Conroe is really 30% faster and IF Intel prices Conroe LESS than the current P4 (P4 costs much more than a comparable Athlon: can you believe it?!?!?) then we may see a battle.
How many people would pay $1000 premium for 30% better speed? Might as well spend them toward a dual (or quad) video card system.

Last, but not least, IMHO, Intel made a mistake sticking to the FSB. It does not seem to be an architecture with future compared to an integrated mem. controller. Maybe it was a matter of patents.

I hope AMD will keep up with Intel ( actually, I hope it'll beat the **** out of them ): these past 2 years we've finally seen low prices for good CPUs: something rare if you ask me.
March 17, 2006 3:24:58 PM

amen Darth_Farter

Best thing for us is major competition between the two. It doesn't really matter if Conroe is top dog or whatever AM2 chip is top dog. We win regardless as they try to beat each other over the head with their latest silicon. I'm happy Intel has such a good chip 'cause it forces competition.

Fritz wins
March 17, 2006 3:28:46 PM

Can't INTEL just take their new PENTIUM D's and LIKE add HT to each of the CORES? Id that possible. Lol i know that INTEL FAns are gonig to jump me and beat me down with logic and TEchnical Impossibilities. But if i had the Money i'd get a Dual CORe with HT and NetBurst with Conroe Arcutucture and AMD's Powersavingnes. yeah i'd have the best of Bothworlds.
March 17, 2006 3:29:58 PM

I actually hope that they will have the memory controller out of the chip, a little bit like the IBM Power5 architecture, each memory bank has it's own controller. AMD would only need to change the memory controller for more HT channels, then connect these memory controllers to the HT.

This would scale the memory without having to wait for the next CPU generation and keep latency at an acceptable level. It would also allow memory raiding, just like an hard disk raid 5 where one bank is a safety for the others. Hot swap memory would then be possible.

This would kick the ass of Intel, really... then again Intel could do the same, instead of putting a full memory controller they would put a simple link to the memory controller.
March 17, 2006 4:35:53 PM

Hyper trading does not scale well with multiple cores (as far as I know).
Conceptually, HT rearranges threads to execute two at the same time in the same core. In order for that to function across multiple cores you'd have to be able to juggle around threads which I think it'll require much more complex integration between cores.
Infact, I think HT is sort of limited when multiple cores are present because sharing the tasks across cores may reduce the chances of being able to have threads to run on the same core.
March 17, 2006 4:50:38 PM

Interesting perspective. Never heard of redundant RAM before.
I think having 4 independent access is in the roadmap for AMD: that pretty much means one controller per bank in most systems today.

The integrated controller theoretically is much faster and requires less idle cycles than an external controller before the data is available to the CPU. I'm sure there is a turning point when the other architecture may be beneficial.
March 17, 2006 6:00:11 PM

Quote:
I actually hope that they will have the memory controller out of the chip, a little bit like the IBM Power5 architecture, each memory bank has it's own controller. AMD would only need to change the memory controller for more HT channels, then connect these memory controllers to the HT.


Actually, AMD's IMC connects to system memory through a dedicated 64-bit bus, which includes the crossbar switch (XBAR), the memory controller (MCT) and the DRAM controller (DCT); no HyperTransport links, here (and, I doubt they'll ever be used for "plain jane" DDRx). Even with serial system memory...

Quote:
This would scale the memory without having to wait for the next CPU generation and keep latency at an acceptable level. It would also allow memory raiding, just like an hard disk raid 5 where one bank is a safety for the others. Hot swap memory would then be possible.


Intel has already implemented this feature (RAID 0) in its FBDIMM AMB (Advanced Memory Buffer) chip. FBDIMM is an Intel protocol; and, works serialy. That would probably fit within the HT specs. But... it's an Intel protocol... (see JEDEC).


Cheers!
March 17, 2006 6:54:10 PM

Quote:
I actually hope that they will have the memory controller out of the chip, a little bit like the IBM Power5 architecture, each memory bank has it's own controller. AMD would only need to change the memory controller for more HT channels, then connect these memory controllers to the HT.


Actually, AMD's IMC connects to system memory through a dedicated 64-bit bus, which includes the crossbar switch (XBAR), the memory controller (MCT) and the DRAM controller (DCT); no HyperTransport links, here (and, I doubt they'll ever be used for "plain jane" DDRx). Even with serial system memory...




They are now using 128bit interface, if I am not wrong, imagine if they want to go to 256 bit interfaces or more, I'd say that's a lot of pins for nothing, the number of rank to be used will always be limited, unless there is some kind of buffers. Routing will get harder and harder while the limit will be the CPU line driver. OK have to say, you are right, could they make this nifty solution, even if it's using a dedicated interface, with low pin count ?

Quote:

This would scale the memory without having to wait for the next CPU generation and keep latency at an acceptable level. It would also allow memory raiding, just like an hard disk raid 5 where one bank is a safety for the others. Hot swap memory would then be possible.


Intel has already implemented this feature (RAID 0) in its FBDIMM AMB (Advanced Memory Buffer) chip. FBDIMM is an Intel protocol; and, works serialy. That would probably fit within the HT specs. But... it's an Intel protocol... (see JEDEC).

Cheers!

I know Intel has this, I tought it was "raid1", The thing is why have real mirroring of memory if someone could have a raid5, increase memory BW and make it fault tolerant. Considering ECC and raid5, it means that the ECC can do it's job, flag the operator and get it fixed. To get a failure the ECC of 2 bank as to be faulty at the same time.

I just think that for motherboard design it would be easier and better. Someone could buy a 8xx and stuff it with memory all around and get a crazy memory BW. OK the latency would be a bit higher, but still better than part of a NB.
March 17, 2006 10:08:11 PM

Quote:
They are now using 128bit interface, if I am not wrong, imagine if they want to go to 256 bit interfaces or more, I'd say that's a lot of pins for nothing, the number of rank to be used will always be limited, unless there is some kind of buffers. Routing will get harder and harder while the limit will be the CPU line driver. OK have to say, you are right, could they make this nifty solution, even if it's using a dedicated interface, with low pin count ?


You're right. 128-bit interface.
As for the pin-count issue you addressed, I don't see, in the near term, drastic improvements: Socket F is going above the 1000 pins' mark (1207, if I'm not mistaken) for up to quad-core (though it's nowhere near IBM's POWER5+ which, like POWER6, has an IMC!); however, for the time being, I believe an IMC still has the advantage over a shared, parallel bus.
Speculating, I think that a fully-programmable IMC would solve a lot of issues... but, is this possible/viable?

Quote:
I know Intel has this, I tought it was "raid1", The thing is why have real mirroring of memory if someone could have a raid5, increase memory BW and make it fault tolerant. Considering ECC and raid5, it means that the ECC can do it's job, flag the operator and get it fixed. To get a failure the ECC of 2 bank as to be faulty at the same time.

I just think that for motherboard design it would be easier and better. Someone could buy a 8xx and stuff it with memory all around and get a crazy memory BW. OK the latency would be a bit higher, but still better than part of a NB.


Right again. RAID 01.
If I understand it correctly, you're referring ECC doing a better job than... RAID 01. If it's the case (and leaving the price issue aside), FBDIMM + AMB has much more to it than just RAID 01 redundancy (it's easy to find FBDIMM specs on the net...).


Cheers!
March 17, 2006 10:11:11 PM

Ah! By the way, hello Finland! ; )
March 18, 2006 2:00:01 AM

Conroe will make you cry that you don't have one. You AMD nutcase brag :D  how good the chip is and here is the response to your chip. Conroe yourself and take it like a man! :D 
March 18, 2006 3:29:43 AM

I doubt they'd be having yield problems, especially on the 512k ones. Demand is high and they're reluctant to make them on 90nm.
March 18, 2006 3:59:31 AM

Yeah, hehe. It would be cost driven.

Conroe is being phased in slowly which was discussed in another thread so the pressure isn't really on, especially with the all cool new things they've got lined up.
March 18, 2006 4:20:42 AM

Can't remember. Here the link to the roadmap. Link.

I agree, seems odd not to. Perhaps they're preparing to get woodcrest out asap?

Thanks. :D 
March 18, 2006 9:55:44 AM

Quote:
And the point is?

And yes, with Conroe they will live up to the hype.



How do you know?

Do you have proof?

Manufacturers make claims all the time and rarely live up to them.

What is so special about the Conroe?

How much is Intel paying you???????????????

Yup. Links or shens. I love how Intel fans usually brag about how good Intel is going to be... after a few years you have to begin wondering when its actually going to happen.. ;) 
March 18, 2006 12:39:43 PM

You must be a newbie to the cpu world. :oops:  8O
March 18, 2006 12:54:10 PM

Respectfully disagree. http://www.newegg.com/ProductSort/SubCategory.asp?SubCategory=343
Single core Athlon 3700+ are running just a tad cheaper than Pentium 4 641 (3.2GHz).
Considering the extra power consumption, the extra cost for cooling and the electricity bill, I think single core, except for the top-of-the-line, is a no brainer.
Even there, Pentium EE 840 and 955 go for ~$900 and ~1000 resp.
For ~800/1000 you get an FX57 or FX60: undoubtely more efficient and faster in all benchmarks except, maybe, encoding.

In the dual core you might be right: Pentium D 840 (3.2GHz) is $358. For $355 you get an X2 4200+ which is just a bit slower (http://www.tomshardware.com/2005/08/01/dual/page12.html).
However, again, the thermal envelope is just a no match for Intel.

As I said, if Conroe delivers what promises at the same price of the Pentium 4, then yes, AMD prices will have to drop. 6 months from now, however, we'll be comparing new, top-of-the-line Intel CPUs with over 1-year old AMD ones (the THG article above is from Aug 1st 2005).

I don't know, like everybody else, if AMD will have something as good or better than Conroe by the end of Q3. My guess/fear is no, however, I'm confident that in early 2007 we'll have some pleasant surprise.

Oh, and by the way, I agree 100% on the 65nm: crucial for the future of AMD.
March 18, 2006 12:57:00 PM

Quote:
AMD tries to tell us a lot of things >_>
ycon shut up geez intel sold us prescott and what happened you loved it cause of your mindless fanboyism. by the way nice find 9-inch :wink: and dudes i'm gone for a day and the forum is still the same ol crap geez :roll:
March 18, 2006 2:22:10 PM

Ok, thanks: i think we're on the same paqe now.
Except I'm still and AMDer :lol: 
!