HyperTransport vs. Common System Interface

As with the 2 others (K10 and Nehalem) let's keep the fanboy crap out of this.

I wanted to get peoples thoughts on Hypertransport vs. Intel's CSI, and whether they think which is better than the other and why. A "Why" isn't "because AMD/Intel sux0rz!", so don't start that crap. I think this might spark some people to dig for info on CSI, as I can't find any real information on the specs or details of the protocol other than it's performance is supposedly about the same as a 1600MHz Front Side Bus (which would put it @ about 12.8GB/s Bandwidth, give or take). Anybody got anything??

~~Mad Mod Mike, pimpin' the world 1 rig at a time
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  1. I'm going to attempt to find more, but I need ma sleep so I'ma peace out :).

    ~~Mad Mod Mike, pimpin' the world 1 rig at a time
  2. Talking about HTT and CSI, only have point when talking about multi-core multi-cpu systems, else both are totaly useless and have no adventages over the today and near future FSB.

    Intel wasted so much time and money on the Netburst to figure out that it is unsucessfull for the current computer technology. Meanwhile AMD used Intels failure to takeover a big portion of the market, therefore improving the K7 architecture and expanding the production capacities.
    HTT was a good invention that offered great connectivity and singificent overall performance increase on the multi-cpu server systems. For the multicore systems HTT have a lot of adventages over FSB, but it is still limited and needs improvement.
    Another successfull improvement was the on-chip integration of the 128bit DDR memory controller. This enabled each Opteron 2xx/8xx to have separate memory system owning independent memory modules that can be shared between the rest Opteron 2xx/8xx processors installed on the current mainboard, thanks to the fast HT links.

    At same time Intel was pushing the Netburst to its death reducing instruction efficiency with every new stage added, while generating more heat for every MHz. But somewhere in the middle of their dream, dissapointed by Prescott, they woke up with the idea of rebuilding the old successfull P3 which research was paused at Tualatin core. Pentium M was born and proved as more successfull than expected. When its update-Yonah came, it was quite clear that Intel is preparing something spectacular to replace their current desktop and server offer. It is the Core architecture, an impressive rework of Yonah, that is better in everything than their rival K8 chips(price, performance at same clock, power consumation). They almost achieved what they wanted and planed. I guess that this architecture will bring them the lost crown of performance desktops.
    Considering that today Intel is mobile computer leader, if they beat Opteron systems that means that AMD is completly out of the game. But, not so fast. AMD have thier weapons: HTT and the IMC(integrated memory controller).
    Intel will need a better technology than these of AMD if they want to be better in the server arena for sure. That mix of both technologies the HTT and the IMC, Intel named as CSI(Common System Interface).
    CSI was started as project that will overperform HTT on every position(latency, bandwidth per pin, operating freqfency, number of links, easyness of implementation, cost), but is not done yet and its late also. It will be able to connect up to 32 cores with 64bit 1600MHz fullduplex links as some sources are saying. CSI will also have an integrated multi-channel DDR2 memory controller. While Intel are quite quiet about CSI it looks like they are having problems releasing this tehcnology. CSI first was supposed to be available for the first release of Core architecture chips, but probably CSI developers need more time in order to make it be better than the future AMD HTT 3. Until than, Intel have a solution for some period. That is independend FSB connection to northbridege for each core, but sharing the memory bandwidth. I guess it will be sucessfull to avoid the bottleneck of memory bandwidth on their first MCM quad-core(Clovertown) chips.
    If they can't success with CSI, there is the option of going across the own ego(like with EM64T aka x86-64) and licensing the well implemented and succesfull AMD HTT.

    some usefull links:
  3. pro HTT: matured technology
    pro CSI: Maybe something revolutionary that HTT cant keep up with
  4. Is HTT 3.0 just changing the lanes from 16bit to 32bit and raising the speed to 1400 full duplex over 1000?
  5. Quote:
    Is HTT 3.0 just changing the lanes from 16bit to 32bit and raising the speed to 1400 full duplex over 1000?

    HTT 2.0 specs are:

    1400MHz (2800MHz Effective)
    32-bit Links (64-bit Effective)

    HTT 3.0 is supposed to double that to 2800MHz (4600MHz Effective)
    64-bit Links (128-bit Effective)

    ~~Mad Mod Mike, pimpin' the world 1 rig at a time
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