This may be the ram of choice for AM2

How do you know? As you have stated many times previously, conroe is not here yet.

How do you know? As you have stated many times previously, conroe is not here yet.

Uhm...you're not listening...the CPU has nothing to do with how fast it can access RAM you Moroff, if the FSB in a Conroe is 1066MHz or 1333MHz, let's do math, shall we?

1333x64/8=10,664MB/s - Max Extreme Edition FSB (Provided Intel can MAKE 3.33GHz Conroe w/ that bus)

800x128/8=12,800MB/s - Max T-Band for DDR2-800

Let's do an A64 for Sh!ts and giggles..

∞*800/8=(-∞,∞ ) Max T-Band. (You do understand Alg2, right?)

~~Mad Mod Mike, pimpin' the world 1 rig at a time

.....Are you stupid?....That is a serious question, are you mentally challenged? I am not joking....

You don't understand anything, and that isn't an insult, but a concern. Please get help immediately.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Math is not an assumption. He's telling you the actual maximum transfer rates of each.

The point he was trying to make is that the maximum transfer rate of Intels FSB at 1333MHz is not even equal to that of DDR2-800, much less DDR2-1000. So the extra speed for an Intel processor is worthless. Now the tighter timings would make a difference though.

You beat me to finishing my edit.

Hehehe, I'm a fast typer (over 110wpm fyi )

I think it's necessary for this too:

An "Expert" is going to come in here and lambast me about Woodcrest, so I have taken the liberty upon myself to shoot them down before they can start:

Woodcrest w/ DIB (2 FSB's):

1333MHzx2=2666MHz (Provided they are Linerally/Striped scaled, which I DOUBT severely). That's 2666x64/8=21,328MB/s Max T-Band, that's farely nice...

Let's look @ the FB-DIMM's it's going to use....

The max channels for FB-DIMM's is Six-Channel, so let's use 1000MHz as our base for this...

1000x384/8=48,000MB/s Max T-Band for FB-DIMM DDR2-1000 (Provided the MC on the NB ever SCALES that high, highly unlikely as well).

So now we got 21GB/s and 48GB/s....hmm....see a problem here?....

Now let's look at a Socket F Dual CPU AMD Opteron 64 setup...

2 CPU's = 2 Memory Controllers (The 1207 pins can allow for almost 4 MC's per CPU, but we won't go there) and thus is now ∞*∞ for Memory Bandwidth limitation....Let's do more math....

48GB/s per Node x2 = 96GB/s Max T-Band for Dual Opty 64's using FB-DIMM DDR2-1000, use NUMA to aggregate the Memory, and you're lookin at REAL-WORLD bandwidth of over 85GB/s....compared to Woodcrest REAL-WORLD of, say, 16GB/s....

Yea.....you see now how the FSB is a PoS....

~~Mad Mod Mike, pimpin' the world 1 rig at a time

interesting math, dude. Nice work.

I agree the FSB is pretty crappy. Have known about it's bad limitations for quite a while. But...

question... why the assumption of 384? or 6*64. What if it is 128? I don't know whether or not it will be 128bit or 64bit. Do you know?

thanks

**UPDATE USING CORRECT FB-DIMM DATA WIDTHS**

Woodcrest w/ DIB (2 FSB's):

1333MHzx2=2666MHz (Provided they are Linerally/Striped scaled, which I DOUBT severely). That's 2666x64/8=21,328MB/s Max T-Band, that's farely nice...

Let's look @ the FB-DIMM's it's going to use....

The max channels for FB-DIMM's is Six-Channel, so let's use 1000MHz as our base for this...

1000x432/8=54,000MB/s Max T-Band for FB-DIMM DDR2-1000 (Provided the MC on the NB ever SCALES that high, highly unlikely as well).

So now we got 21GB/s and 54GB/s....hmm....see a problem here?....

Now let's look at a Socket F Dual CPU AMD Opteron 64 setup...

2 CPU's = 2 Memory Controllers (The 1207 pins can allow for almost 4 MC's per CPU, but we won't go there) and thus is now ∞*∞ for Memory Bandwidth limitation....Let's do more math....

54GB/s per Node x2 = 108GB/s Max T-Band for Dual Opty 64's using FB-DIMM DDR2-1000, use NUMA to aggregate the Memory, and you're lookin at REAL-WORLD bandwidth of over 95GB/s....compared to Woodcrest REAL-WORLD of, say, 16GB/s....

Yea.....you see now how the FSB is a PoS....

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Owned.

Math is not an assumption. He's telling you the actual maximum transfer rates of each.

The point he was trying to make is that the maximum transfer rate of Intels FSB at 1333MHz is not even equal to that of DDR2-800, much less DDR2-1000. So the extra speed for an Intel processor is worthless. Now the tighter timings would make a difference though.

True. I have a slight divergence - isn't math technically theoretical? I remember hearing that somewhere...

2+2=4...but could it be 65???? Hmm...Nope, it's 4.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Good question, let me go find out.

EDIT: Found out, it is 72-bit, I'll post again with updated speeds.
EDIT2: The FSB is still 64-bit (IIRC) but FB-DIMM's are 72-bit, which means it's even WORSE than what I posted, LOL.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

yeah... cuz the FSB still runs at 21GBs/sec it just really sucks....

DDR2-800 is already overkill, I wouldn't recommend anything above DDR2-667 unless you're overclocking.

Another thing to note, in a Dual CPU Woodcrest, CPU Coherency also has to eat away the bandwidth of the FSB.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Hmm...interesting theory, but I am positive it is false because the Memory Controller bus is independent of HyperTransport and the fact that I can lower HTT to 600MHz (1200MHz effective) and still get RAM bandwidth exceeding HTT bandwidth, and therefore, infinity is only because it's as fast as your RAM is.

What is this 2 accesses/cycle? HTT is 1GHz, 16-bit Links Full Duplex (2GHz 32-bit Data Width), and that means 8GB/s Total.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

Most people don't include the 2nd 1GHz Link as they say "it's just marketing", but if you do the math, without that 2nd link (it's 1 link, but Full Duplex, so really the 2nd Plex) it's not right:

1GHz Full Duplex = 2000MHz

2000x32/8=8000MB/s Bandwidth

Each Plex is 16-bit 1000MHz, and both are absolutely required for this speed of the FSB, so the FSB IS 2GHz.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

interesting link....

I thought something was a little one sided about the FSB/memory controller deal. They're gonna take care of the FSB problem just fine.

That's hilarious.

The 64 vs 72 bit difference on the RAMs is for any potential ECC.

The link from CPU to NthBrj/FSB does not require it.

The link from NthBrj/FSB to RAM does though (just in case it is present, assuming the chipset supports ECC in the 1st place).

If Intel fatten the FSB it will help them significantly, they'll need to make CPUs with higher pin counts though, ditto with Northbridge.

Even a 96 bit wide link to the northbride could get them to 12.8 GB/sec (inclusive of overheads), which is ample in most cases. The link could be split into 3 x 32 bit 'buses' each half-duplex, so reads and writes to/from the MCH (NorthBridge) could be performed at once.

Or more ideally a 128 bit wide link to MCH, split into 2 x 64 bit links for somewhere in the window of 12.8 GB/sec to 21.3 GB/sec.

As memory sub-system performance approaches 16 GB/sec the bottleneck becomes the processor. (At least for todays processors, in 10 years the numbers will rise). Even a fration of this with enough prefetching will suffice fine in most applications, including games.

A large database sitting in physical memory would benefit from more. But little else would.

Remember that 20% of the code does 80% of the work, with enough cache and look-ahead / branch prediction, etc latency becomes less and less important.

Reading just 256 bytes (or any block larger than this) from memory, one is better off with higher clocked memory, than lower latency, lower clocked memory. As this is prefetched before required the latency is very effectively 'hidden'.

When/If we have CL6 RAM, going to CL7 won't seam like such a big deal for the clock speed gains.