AM2 bandwidth problems....explained?

[BaronMatrix]

As everyone knows AM2 is a lot less efficient in extracting bandwidth from DDR2 and it made me wonder about something concerneing memory dividers.

Most 939s are CPU speedmultiplier, but if AMD increases HTT to 333MHz and not 400MHz, then they will have an issue the the divider because DDR 800 is not a multiple of 333, so I was wondering if anyone has any info on how they are handling this issue.

 

[MadModMike]

As everyone knows AM2 is a lot less efficient in extracting bandwidth from DDR2 and it made me wonder about something concerneing memory dividers.

Most 939s are CPU speedmultiplier, but if AMD increases HTT to 333MHz and not 400MHz, then they will have an issue the the divider because DDR 800 is not a multiple of 333, so I was wondering if anyone has any info on how they are handling this issue.

The speeds of HyperTransport and that of Memory can be independent of one another, such as having a base HTT of 333MHz and have memory run @ 400MHz is VERY possible, and plausible. AMD, if they plan to run 333MHz HTT (Rumored 400MHz for FX's) than they can EASILY run the Memory Bus @ 400MHz or higher (For such as DDR2-1066) and not run into problems that Intel based platforms may.

BTW, that "inefficiency" is due to the Modules and ES, expect better results in the future on launch day.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[K8MAN]

I will be dissapointed by AM2 if there isnt @ least a 10-15% increase with DDR2 1066.

 

[MadModMike]

I will be dissapointed by AM2 if there isnt @ least a 10-15% increase with DDR2 1066.

If you get 4-4-4-12 DDR2-1066 (It DOES exist IIRC) than it will offer vast improvements in performance, it will nullify the latency due to higher bandwidth.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[BaronMatrix]

As everyone knows AM2 is a lot less efficient in extracting bandwidth from DDR2 and it made me wonder about something concerneing memory dividers.

Most 939s are CPU speedmultiplier, but if AMD increases HTT to 333MHz and not 400MHz, then they will have an issue the the divider because DDR 800 is not a multiple of 333, so I was wondering if anyone has any info on how they are handling this issue.

The speeds of HyperTransport and that of Memory can be independent of one another, such as having a base HTT of 333MHz and have memory run @ 400MHz is VERY possible, and plausible. AMD, if they plan to run 333MHz HTT (Rumored 400MHz for FX's) than they can EASILY run the Memory Bus @ 400MHz or higher (For such as DDR2-1066) and not run into problems that Intel based platforms may.

BTW, that "inefficiency" is due to the Modules and ES, expect better results in the future on launch day.

~~Mad Mod Mike, pimpin' the world 1 rig at a time


Thx, Mike. I told them all you weren't an a-hole. j/k. anyway, I was just curious if the divider would be affected if HTT was at 333MHz. I also noticed that I don't remember seeing the Anand tests mention the faster HTT. Do you know if the chip he used was at 200 or 333?

 

[MadModMike]

As everyone knows AM2 is a lot less efficient in extracting bandwidth from DDR2 and it made me wonder about something concerneing memory dividers.

Most 939s are CPU speedmultiplier, but if AMD increases HTT to 333MHz and not 400MHz, then they will have an issue the the divider because DDR 800 is not a multiple of 333, so I was wondering if anyone has any info on how they are handling this issue.

The speeds of HyperTransport and that of Memory can be independent of one another, such as having a base HTT of 333MHz and have memory run @ 400MHz is VERY possible, and plausible. AMD, if they plan to run 333MHz HTT (Rumored 400MHz for FX's) than they can EASILY run the Memory Bus @ 400MHz or higher (For such as DDR2-1066) and not run into problems that Intel based platforms may.

BTW, that "inefficiency" is due to the Modules and ES, expect better results in the future on launch day.

~~Mad Mod Mike, pimpin' the world 1 rig at a time


Thx, Mike. I told them all you weren't an a-hole. j/k. anyway, I was just curious if the divider would be affected if HTT was at 333MHz. I also noticed that I don't remember seeing the Anand tests mention the faster HTT. Do you know if the chip he used was at 200 or 333?

Having a Memory divider, in my experience with AMD64's, DOES affect performance, but positively. But, by this I mean setting a RAM divider BELOW that of the HTT speed, this has proven to give larger inprovements in Memory Write speeds, while maintaining the same average Memory Read speeds as 1:1. If the divider is changed from 1:1, it will NOT affect the A64 negatively AT ALL, at best, it will change it positively, and at worst, it won't affect it at all.

The rumor was that AMD would run the AM2's of Windsor (the X2's and A64's) @ 333MHz Base while the FX's @ 400 (To run DDR2-667 and DDR2-800 respectfully) I still have not seen conclusive evidence of either one, though the ES of Toms back in February I believe were running 200MHz, though I am not positive.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[MadModMike]

AFAIK, C51XE+MCP55PXE, MCP55P SLI, MCP55 Ultra and MCP55S will all have up to 200Mhz HTT official support only on lauch day.

That's what I figured, it would coincide with HT 1.05 than. I suspect the Socket 1207's would be the only ones to increase HT Base, even if that.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[BaronMatrix]

AFAIK, C51XE+MCP55PXE, MCP55P SLI, MCP55 Ultra and MCP55S will all have up to 200Mhz HTT official support only on lauch day.

Interesting. There was a lot of talk about the higher speed HTT. I wonder what happened. It actually seems reasonable that the higher BW of DDR2 would need a fatter pipe than 200MHz, but I'm not sure. I'm curious though.

 

[MadModMike]

AFAIK, C51XE+MCP55PXE, MCP55P SLI, MCP55 Ultra and MCP55S will all have up to 200Mhz HTT official support only on lauch day.

Interesting. There was a lot of talk about the higher speed HTT. I wonder what happened. It actually seems reasonable that the higher BW of DDR2 would need a fatter pipe than 200MHz, but I'm not sure. I'm curious though.

As I said, the Memory will coincide with the RAM and can be independent of HT Speed, so if you have DDR2-800 and the base Memory is 400MHz, than if you run DDR2-667, it will probably lower the Memory to that of DDR2-667 (333MHz) and if you throw in DDR2-1066 (533MHz) than it will likely be that you'll have to OC or set a RAM Divider in the BIOS, these are alot of important questions that I think deserve answering.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[theaxemaster]

So if I read this correctly, its currently at 200x5 and they're upping it to 333x5 or 400x5, depending on which one you buy. correct? And the HT bus matching the memory clock doesn't change performance appreciably?

I don't remember if the benches we've seen so far were using the 400 HT bus. I'm almost certain that Intel's comparison used an FX at 200 since I doubt the current chips can OC that far, or that intel would do it in their comparison. It'll be interesting to see the gains from the HT increase.

 

[MadModMike]

So if I read this correctly, its currently at 200x5 and they're upping it to 333x5 or 400x5, depending on which one you buy. correct? And the HT bus matching the memory clock doesn't change performance appreciably?

I don't remember if the benches we've seen so far were using the 400 HT bus. I'm almost certain that Intel's comparison used an FX at 200 since I doubt the current chips can OC that far, or that intel would do it in their comparison. It'll be interesting to see the gains from the HT increase.

There is no 333MHz or 400MHz HT, that was a rumor and is proven to be false (so far). If you're referring to Intel IDF of FX vs. Conroe, those "benchmarks" are more laughable than a 1 legged man in an ass kicking competition.

~~Mad Mod Mike, pimpin' the world 1 rig at a time

 

[old_times]

laughable than a 1 legged man in an ass kicking competition

 

[BaronMatrix]

So if I read this correctly, its currently at 200x5 and they're upping it to 333x5 or 400x5, depending on which one you buy. correct? And the HT bus matching the memory clock doesn't change performance appreciably?

I don't remember if the benches we've seen so far were using the 400 HT bus. I'm almost certain that Intel's comparison used an FX at 200 since I doubt the current chips can OC that far, or that intel would do it in their comparison. It'll be interesting to see the gains from the HT increase.

There is no 333MHz or 400MHz HT, that was a rumor and is proven to be false (so far). If you're referring to Intel IDF of FX vs. Conroe, those "benchmarks" are more laughable than a 1 legged man in an ass kicking competition.

~~Mad Mod Mike, pimpin' the world 1 rig at a time


ROTFLMAO

But anyway I think this maybe why AM2 didn't show the gains I expected. The divider issue really difficult because 1066x2 = 2133; 1066x3 = 3200; etc. Looking for the correct ratio is a bitch though. Even at 533 you get some wierd ratios but they have to be whole numbers. It seems like they have to pull an Intel and run different classes of chips at different HT speeds to use different DDR2 speeds.


Maybe we can get Tom to find out.

 

[crazywheels]

its not even out yet, i wouldn't even get your panies in a bunch just quite yet

 

[ltcommander_data]

I'm not sure how the dividers are an issue. Correct me if I'm wrong, but I thought current processors can operate with DDR333 while maintaining the 200MHz base HT speed. If they have dividers to do the 200MHz to 166MHz ratio now, I don't see why a 333MHz (HT) to 400MHz (DDR2) divider is an issue and would be responsible for the lack of bandiwdth efficiency. Besides, as MadModMike already said, current indications are that Rev F will continue to use the 200MHz base HT. They're probably saving 333MHz for K8L to allow better product differentiation next year.

It actually seems reasonable that the higher BW of DDR2 would need a fatter pipe than 200MHz, but I'm not sure. I'm curious though.

As I'm sure you know, with an OMC the memory talks directly with the processor anyways so the processor doesn't need to concern itself with the HT bandwidth limiting memory bandwidth. The only issue would be whether HT is wide enough for the rest of the system, which the 200MHz x 5 should be considering most previous FSB CPU - Northbridge traffic was MC related which no longer exists. I don't believe there was much real world benefit from going 800MHz to 1000MHz so the HT link is hardly full right now.

 

[BaronMatrix]

I'm not sure how the dividers are an issue. Correct me if I'm wrong, but I thought current processors can operate with DDR333 while maintaining the 200MHz base HT speed. If they have dividers to do the 200MHz to 166MHz ratio now, I don't see why a 333MHz (HT) to 400MHz (DDR2) divider is an issue and would be responsible for the lack of bandiwdth efficiency. Besides, as MadModMike already said, current indications are that Rev F will continue to use the 200MHz base HT. They're probably saving 333MHz for K8L to allow better product differentiation next year.

It actually seems reasonable that the higher BW of DDR2 would need a fatter pipe than 200MHz, but I'm not sure. I'm curious though.

As I'm sure you know, with an OMC the memory talks directly with the processor anyways so the processor doesn't need to concern itself with the HT bandwidth limiting memory bandwidth. The only issue would be whether HT is wide enough for the rest of the system, which the 200MHz x 5 should be considering most previous FSB CPU - Northbridge traffic was MC related which no longer exists. I don't believe there was much real world benefit from going 800MHz to 1000MHz so the HT link is hardly full right now.


I'm still curious as to how that's going to work DIVIDER WISE because A64 memory speed is calculated by CPU speed/multiplier afaik.

 

[ltcommander_data]

http://www.cpuid.com/reviews/K8/index.php

If you scroll down a bit they have a nice chart of the current dividers in place for the various clock speeds. The DDR400 speeds obviously work out nicely at 200MHz, but the DDR333 numbers can fluctuate quite a bit. I believe the AM2 samples they use are 2.4GHz models with a 200MHz HT bus so I would expect a divider of 6 for 400MHz and a divider of 7 for 343MHz, which is close enough to DDR2 667.