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AMD and Intel. You got Questions, we got Answers.

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April 23, 2006 11:49:25 PM

I intend this to be the "question and answer thread," for JumpingJack's IBM, Intel and AMD comparison thread: http://forumz.tomshardware.com/hardware/Process-Manufac... . Post your questions here about their techniques. We will try to answer your questions to the best of our ability.

More about : amd intel questions answers

April 23, 2006 11:51:43 PM

Alright, Chief! :lol: 


Cheers!
April 24, 2006 3:33:42 AM

This thread doesn't seem to be very successful. Alas, not every thread can be a blockbuster :)  .
Related resources
April 24, 2006 3:37:32 AM

Quote:
I intend this to be the "question and answer thread," for JumpingJack's IBM, Intel and AMD comparison thread: http://forumz.tomshardware.com/hardware/Process-Manufac... . Post your questions here about their manufacturing techniques. We will try to answer your questions to the best of our ability.



When I have question, I ask Google.. No need for another thread about AMD and Intel shit...
April 24, 2006 3:46:39 AM

Quote:
I intend this to be the "question and answer thread," for JumpingJack's IBM, Intel and AMD comparison thread: http://forumz.tomshardware.com/hardware/Process-Manufac... . Post your questions here about their manufacturing techniques. We will try to answer your questions to the best of our ability.



When I have question, I ask Google.. No need for another thread about AMD and Intel shit... No wonder this thread isn't going anywhere, the public don't like it Joset! It burns :cry:  . Oh well.
April 24, 2006 4:32:06 AM

my 1st question: what is the possible limit, in terms of nm. we all know by quantum physics u cannot scale down forever.
2nd question: what progress do we have in optical computing so far?

i don't think u need to post all those academic details. some people won't face the fact even it is in front of them. they will turn back and say " oh, i didn't see".

here are some simple facts up to this day:

intel lead in MANUFACTURING TECHNOLOGY to the rest of the world by 9-12 months. larger wafer, better yield(even under same 90nm) and smaller gate. that should give intel some advantage in price but too bad we didn't see that because intel was too greedy.

amd lead in cpu design. amd's 64bit solution is WAY better than intel's. as for 32bit computing, FX60 is still the fastest one!

i think the future is not belong to them, neither intel nor amd. it will belong to some smaller company whoever 1st get optical computer into market. it will be at least 100 faster.
April 24, 2006 4:38:31 AM

Either It's IBM (the people wo Invented the Computer itself) or it might be the (Peek'a'boo) company VIA
April 24, 2006 5:03:58 AM

What is your take on SOI?
April 24, 2006 5:26:31 AM

thanks for the answer.
i only remember tiny part of solid state physics i learned 20 years ago. but mostly just names, cannot remember those equation at all.
I hate Dirac symbol. i almost failed in quantum mechanics.
lol

ah oh. it meant to reply Jack, not endyen. sorry 4 that.
April 24, 2006 6:03:12 AM

I knew that, and I'm sure Jack did as well. No problem.
It is nice that you included the correction though. We could use more manners around here sometimes.
(not always though. If you are a corporate fanboy, dont expect me to be polite, the only fanboy I like are performance or price/performance)
April 24, 2006 7:54:54 AM

I'm beginning to get the impression that SOI and NiSi2 are mutually exclusive, ( the oxides in SOI would likely cause NI migration) Is that right?
April 24, 2006 8:09:30 AM

The only thing I know is that SOI-based process is 3-4 times more expensive than non-SOI ones...
April 24, 2006 10:33:41 PM

I see this thread isn't so bad after all, people are getting something out of it. 8)
April 24, 2006 11:16:16 PM

Quote:
I see this thread isn't so bad after all, people are getting something out of it. 8)


Well, I surely hope you're right. I don't intend to help pile up posts in JumpingJack's main thread, unless when pertinent.


Cheers!
April 25, 2006 12:11:50 AM

Quote:
Either It's IBM (the people wo Invented the Computer itself) or it might be the (Peek'a'boo) company VIA


I'd be REALLY surprised if VIA made it

Quote:
Quantum Mechanical Tunneling

Interesting....if you have any links (specially Quantum Mechanical Tunneling for Dummies) it would be nice if you posted it (or at least pm me with that :p )

Quote:
I hate Dirac symbol

I hate Nabla
April 25, 2006 1:45:15 AM

Quote:

NOW: Check back and I will give a less mathematical, less abstract explanation of the phenomena after I have had some coffee, kissed the wife, and watched some news. :)  ....
Jack

Ty jack, BTW, do you know what is total pupm4g3?
Coffee + Red Bull + Coke + Lotsa sugar (after 8 big mugs of coffee or so in 3-4 hours)

I drank that broth of 3vil to complete a research project (very ambitious indeed, 25 measured spots, about 10 parameters, measured for two hours with 1 minute gaps, the analysis of that huge amount of data was made by only 3 people in a weekend + 2 additional days of WORTHLESS 3dmodelling a "1:1" model of 20+ blocks with every building in a P-I 233mhz 64Mb EDOSIMM...), man, lemme tellya, pure power, like:

:x :arrow: :cry:  :arrow: :(  :arrow: :o  :arrow: 8) :arrow: 8O

Use it only when is absolutely necessary

If someone could make an electronic equivalent, 20Thz speeds would seem like 20Mhz right now xD

Sorry for getting sooooo out of the thread :p 
April 25, 2006 3:05:41 AM

Well, I read the links and more or less got the idea (except for shroedinger...) but now I "understand"

That's part of the Unified Field Theory, try to relate gravity, electromagnetism, nuclear forces, newtonian physics and quantum physics into one giant block of nifty things, related one with another

The problem is, as you said, that stuff behaves differently at different scales, the most obvious example is if the electric force that tries to break away an atom's core is greater than the gravitational force that attracts them, how is it possible that the atom stays stable instead of collapsing? The answer: Quantum Chromodynamics, in which the "color charges" act in the phemtometer (¿?) scale and the quarks that make a proton are attracted to each other with such an intensity that it counters the repulsive electric force between protons (bout 30x proton-proton gravity pull)

Another interesting phenomena is time "expansion" the problem is that the object necessary to measure that would be so big that it coudn't achieve a speed close enough to lightspeed to experience it :p 

Here's an interesting link http://www.newscientistspace.com/article/mg18925331.200...
hpoe you like it

Nothing related to the thread, but it's kinda interesting

Oh, and the tunnelling stuff, is it related with the "cloning photon" phenomena? I think not, but I want to be sure
April 28, 2006 5:53:13 PM

Now as Intel has introduced its 45nm chip, what are the main differences as compared with 65nm chip, as they've increased the numbers of transistors... > 1B wot are the real inner changes they've made to the 45 nm chip?
April 29, 2006 1:22:29 AM

Quote:
Now as Intel has introduced its 45nm chip, what are the main differences as compared with 65nm chip, as they've increased the numbers of transistors... > 1B wot are the real inner changes they've made to the 45 nm chip?


45 nm technology is hard to call right now. Let's take details of Intel's current 65 nm technology then speculate on the 45 nm technology. The 65 nm technology has some interesting features that are second generation from the 90 nm technology. Single layer stress liner, NiSi, embedded SiGe stressor, 1.2 nm gate thickness.

For a detail, some pictures and data, see this IEDM presentation
ftp://download.intel.com/technology/silicon/65nm_logic_...

In 45 nm, Intel has been extraordinarily hush hush other than to demonstrate functional SRAM, and specify SRAM bit-cell size, we do not know much about what is going into it. You can bet that SiGe is going to be in it's 3rd generation, stress liner will likely not be a factor after 65 nm as this stress methodology will run out of steam. There has been some hubbub about fully silicided gate electrode (FUSI)

ftp://download.intel.com/technology/silicon/FUSI_transi...

This is needed to get better gate electrode properties, the current poly gate electrode used by both Intel and AMD will not be feasable at the 45 nm node.

Now the advantage from going to 90 nm to 65 nm in the industry is driven more by size than by performance. The performance curve is flattening out using conventional CMOS techniques, however, looking at the FUSI data the 65 nm to 45 nm transition may actually see a leap to 5, 6 or even 10 GHz transistors -- this would be cool :)  ....

Jack

SOI rules all Intel is stupid for waiting till 0.032u before useing it.
April 29, 2006 2:48:58 AM

Quote:
SOI rules all Intel is stupid for waiting till 0.032u before useing it.


Well, I doubt they're stupid at all.

Anyway, this Professor Krishna Saraswat (from Stanford University) has a wonderful collection of slide presentations, in a non-exhaustive, non-purely technical fashion on techniques, materials, processes, you name it, which I particularly like. Here's one regarding not-so-futuristic approaches to computing processes:
http://www.stanford.edu/class/ee311/NOTES/Future%20Devices.pdf

As a side note, both Intel & IBM are more buried in these papers than the oxide itself... :wink:


Cheers!
April 29, 2006 2:54:42 AM

Quote:
SOI rules all Intel is stupid for waiting till 0.032u before useing it.


Well, I doubt they're stupid at all.

Anyway, this Professor Krishna Saraswat (from Stanford University) has a wonderful collection of slide presentations, in a non-exhaustive, non-purely technical fashion on techniques, materials, processes, you name it, which I particularly like. Here's one regarding not-so-futuristic approaches to computing processes:
http://www.stanford.edu/class/ee311/NOTES/Future%20Devices.pdf

As a side note, both Intel & IBM are more buried in these papers than the oxide itself... :wink:


Cheers!

Word.
April 29, 2006 3:00:03 AM

Quote:



SOI rules all Intel is stupid for waiting till 0.032u before useing it.


Well, I doubt they're stupid at all.



Actually I think they were taking a jab at the HORDE
April 29, 2006 3:13:55 AM

Quote:
SOI rules all Intel is stupid for waiting till 0.032u before useing it.


Well, I doubt they're stupid at all.

Anyway, this Professor Krishna Saraswat (from Stanford University) has a wonderful collection of slide presentations, in a non-exhaustive, non-purely technical fashion on techniques, materials, processes, you name it, which I particularly like. Here's one regarding not-so-futuristic approaches to computing processes:
http://www.stanford.edu/class/ee311/NOTES/Future%20Devices.pdf

As a side note, both Intel & IBM are more buried in these papers than the oxide itself... :wink:



Cheers!

Ha, you've been doing some homework :)  Good for you.... you have always had my respect. Nice job.

He can't tell if I am serious or not *cackles manically*.
April 29, 2006 3:21:54 PM

Quote:
Ha, you've been doing some homework :)  Good for you.... you have always had my respect. Nice job.


Yes... been busy (professionally) and also been dealing with two papers you provided:

http://www.virginiasemi.com/pdf/BasicCrystallographicPropertiesofSi.pdf
and
"D. J. Frank, 'Power-constrained CMOS scaling limits'".

Both are very enlightening papers; I'm much more elucidated about [Silicon] crystallography & cleavage planes (Miller indices) & all. Let's see if this «...simple linear interpolation as a function of composition.» (strained Silicon) between the Si lattice constant (5,43 Angs) and the Ge (5,66 Angs) has any influence on SiGe cleavage planes.
This is really fascinating! Pitty is that I don't have the time (nor the basic knowledge...) to go much further... consistently.

(This might seem a bit contradictory but, as a free-lance designer, I'm mostly unemployed; working peaks might take several weeks, though!).

Well, Jack, the respect & consideration is mutual.

And now, back to homework & to those crazy ideas! :D 


Cheers!
April 29, 2006 3:30:35 PM

Quote:
SOI rules all Intel is stupid for waiting till 0.032u before useing it.


Quote:
Well, I doubt they're stupid at all.


Quote:
He can't tell if I am serious or not *cackles manically*.


Sorry to have made you "cackling manically". :lol: 
You're right, Spud; sometimes I miss the irony...


Cheers!
April 29, 2006 3:40:25 PM

Jack is really putting on a show in his thread over there.
April 29, 2006 5:16:25 PM

Quote:
SOI rules all Intel is stupid for waiting till 0.032u before useing it.


Quote:
Well, I doubt they're stupid at all.


Quote:
He can't tell if I am serious or not *cackles manically*.


Sorry to have made you "cackling manically". :lol: 
You're right, Spud; sometimes I miss the irony...


Cheers!

Word.
April 29, 2006 5:41:56 PM

Quote:
Jack is really putting on a show in his thread over there.


Thanks fot the info. I've been through it, already... and, I'm all hears! :wink:

By the way, is the "Unofficial Conroe/AM2 Discussion Thread" down? I can't seem to link into it through my e-mail...


Cheers!
April 29, 2006 6:36:53 PM

fantastic reading I tell you ! hmm Intel has on its roadmap 32nm is that when we will be driving 10Ghz chips ? I can hardly wait (probably 5 years from now....)
April 29, 2006 6:38:58 PM

Quote:
Jack is really putting on a show in his thread over there.


Thanks fot the info. I've been through it, already... and, I'm all hears! :wink:

By the way, is the "Unofficial Conroe/AM2 Discussion Thread" down? I can't seem to link into it through my e-mail...


Cheers! EDIT: Never mind, I bumped it.
April 29, 2006 6:44:12 PM

Quote:
Jack is really putting on a show in his thread over there.


Thanks fot the info. I've been through it, already... and, I'm all hears! :wink:

By the way, is the "Unofficial Conroe/AM2 Discussion Thread" down? I can't seem to link into it through my e-mail...


Cheers! WHAT?!?! NOOO! That is the most widely viewed thread, it can't go! :evil: 

It's not gone, I found it :)  .... I plan on posting some thought to it in the next few days. But have you noticed, a hand full of the all-caps 9-inch posts are locked....I wonder why...
Jack Because people weren't posting anything in relation to the subject.
April 29, 2006 7:23:14 PM

I have a little question (maybe it's stupid, but I can't get over it): Why is the 2001 displayed on my AMD64 CPU (Copyright@2001 AMD)? Did the AMD copyrighted the 'AMD64' text in 2001 (which I think it's unrealizable) or he copyrighted the technology (?????) in 2001, or (even worst :lol:  ) my CPU was made in 2001...
Please give me some oppinion.
April 29, 2006 7:25:17 PM

Quote:
I have a little question (maybe it's stupid, but I can't get over it): Why is the 2001 displayed on my AMD64 CPU (Copyright@2001 AMD)? Did the AMD copyrighted the 'AMD64' text in 2001 (which I think it's unrealizable) or he copyrighted the technology (?????) in 2001, or (even worst :lol:  ) my CPU was made in 2001...
Please give me some oppinion.
I believe it is when that chip was manufactured. Not the model, the chip itself.
April 29, 2006 7:38:03 PM

JACK i have 2 questions.

1)How many cores can theoretically co-exist in one chip?



2)What about the future?I have read somewhere that computers as we know them today will extinct and that the future is quantum computers with infinite bits.What do u think?





ps I must say that i am very impressed with your knowledge
April 29, 2006 7:55:50 PM

Quote:
JACK i have 2 questions.

1)How many cores can theoretically co-exist in one chip?



2)What about the future?I have read somewhere that computers as we know them today will extinct and that the future is quantum computers with infinite bits.What do u think?





ps I must say that i am very impressed with your knowledge
Yes Jack is an extremely intelligent circular desserting device (cookie, :lol:  ).
April 29, 2006 8:01:22 PM

Quote:


ps I must say that i am very impressed with your knowledge


Thanks, I have studied this for 15 going on 16 years in all. :)  ... uArch is not really my forte' but the science and engineering of silicon and transistors I have pretty well mastered.

Jack 8O
April 30, 2006 1:19:00 AM

Quote:
Part I: Introduction – Separating Microarchitecture from Process

(...)

Author's Note: For example, I never fully understood why a deep pipeline allowed for better clock scaling while sacrificing power, but in my endeavor to obliterate your assumption, I found the answer – this is a good example of some of the benefits derived from projects like this, I learn something new each time!

(...)

Ref 5:

Microprocessor performance depends on its frequency and IPC. Higher frequency is achieved with process, circuit, and microarchitectural improvements. New process technology reduces gate delay time, thus cycle time, by 1.5 times. Microarchitecture affects frequency by reducing the amount of work done in each clock cycle, thus allowing shortening of the clock cycle.

Historically, there were two schools of thought on how to achieve higher performance. The “Speed Demons” school focused on increasing frequency. The “Brainiacs” focused on increasing IPC [13], [14]. Historically, DEC Alpha [15] was an example of the superiority of “Speed Demons” over the “Brainiacs.” Over the years, it has become clear that high performance must be achieved by progressing in both vectors
(see Fig. 4)


(Not having had the time to go through the whole paper), I always stumbled at this same question, regarding the execution pipeline: How come you achieve a higher frequency with an adjective (deeper)? The second half of the question seemed more straightforward: Increasing frequency, increases power dissipation (among other variables).
Of course, it is the other way around: Process & uArch (aaarrrggg!) allow for, respectively & as stated, 1.5 reduced cycle time and less work done per cycle, shortening the clock cycle.
Now, the issue is: "...progressing in both vectors..." (wider uArch - higher IPC - more work done per cycle) & (process & circuit... improvements) seem to be incompatible with deeper pipelines. Or, due to Process & uArch improvements, the inevitability of frequency scale up will bring, once more, improved NetBurst-like deep pipelines?


Cheers!
April 30, 2006 9:30:56 AM

Why?
I think that we all agree that Intel made the wrong choice, when they chose speed over smarts. Why then do you say
Quote:
AMD chose the low road, that is mitigate the IPC decline in the face of slowing clock speeds, which I will argue is more out of necessity, discussed below and in more detail

After all, it was the right choice.
Could they have gone the pipeline route?
Since thier performance was better than Intels at the time, there was no hurry. Could they have even gone to a median pipeline setup? It would have given them slightly more speed, but poorer IPC.
Hindsight says they made the right choice.
Tradition says you give people who made smart decisions, the benefit of the doubt.
You have made a very good point, that process and marchitecture are seperate. You say that netburst was a bust. but the process was a win.
And yet, prescott's problem was not only tied to it's poor performance.
One of the most damning comments made about scotty was that he doubled as a space heater. Is that not a process failure?
Sure the transistors in Intel's chips are very fast. The only problem is that they are very fast. To be that fast takes a lot of current, and that means watts. Aside from that, Intel doesn't want people to be able to OC. It slows sales down. I would say that maybe those transistors are a little too fast for thier own good.
On the other hand, AMD has mated thier marchitecture to a transistor that is not too hot, nor too cold (says Goldilocks)
Why do I think the better process is the one that melds best with it's marchitecture? Have you ever thought that perhaps AMD does not have faster transistors because they dont need or want faster transistors?
For me, strapping on a jet engine is not the best process. YMMV.
April 30, 2006 9:38:36 AM

Okay Jack i've got another question for you
Can you explain what actually does Bus/Core Ratio means? and is it true that "lesser is better" or the opposite? i've seen some CPU with higher clock speeds have more BUS/CORE ratio than the lesser clock speed CPUs?
April 30, 2006 5:46:30 PM

the lesser the better?
April 30, 2006 7:08:58 PM

okies... thanx for the insight provided! you are a teacher or wot? you really got the technique to make people understand things... nice work!
April 30, 2006 7:28:42 PM

wOw... ahan... but i have no intrest in Chemistry, i'm in "Artificial Neural Networks" field... anywayz... need some parallel processing here eheh anywayz... thanx for answering my questions...
April 30, 2006 10:19:00 PM

Quote:
okies... thanx for the insight provided! you are a teacher or wot? you really got the technique to make people understand things... nice work!

Unfortunately, many think I am just full of it. Hopefully they will come around... and you are welcome...more than happy to answer your questions.

Also, I do teach on the side, sorta my night job...not this particular subject matter, but chemistry yes. Small community college type work....

Jack **Chokes while trying to simultaneously cough, snort and laugh** You're joking right? Going by how much you help people, one can only draw to a conclusion similar to you being one of the most intellectual people on the "Forumz," :? .
April 30, 2006 11:22:12 PM

Are you again missing the point?
Marchitecture and process are supposed to be complementary. AMD's fit well together.
You may well be able to prove that AMD's transistors can not switch as quickly as Intel's. That is not the point. AMD has invested thier time in balancing process and m-arch. They have been very successfull.
It was Intel's choice to go the speed route. At that point, it became the responability of the process team to supply the transistors that enabled a speed format.
Whether the FX60's transistors can run at 3.8ghz is irrelevant. That is not thier function. It is however the function of the Intel product. They do it, but at a major price. Not only does the increased heat adversly affect the user, it also shortens the life of the silicon itself.
I do not blame the process for the failings of the m-arch. I do however, expect the process to live up to it's share of the load. Intel needed transitors that could run at high speed. They also needed transistors that could do so without putting out a lot of heat.
It is my understanding that with C1 stepping, they will have achieved that.
Finally, Intel's process will be holding up it's end of the bargain.
April 30, 2006 11:49:41 PM

Well, this is a bit off topic but... it's definitely worth it. It's a web lecture by Paul Haljan (WLAP - University of Michigan) on Quantum Computing... and, it's one of the funniest, most enjoyable & enlightening live talks I've been through! A lot seems to obey Murphy's law, including Haljan's unease posture but... better see for yourself! (mind the slide show!).

http://esmane.physics.lsa.umich.edu/wl/umich/phys/satmorn/2004/20041030-umwlap001-01-haljan/real/f001.htm

And, Jack, if you care to have a peak... it's a worthy lecture, in all respects!

Just fabulous! :lol: 



Cheers!
May 1, 2006 6:49:00 AM

First off, I suspect that Intel will be using a modified process on conroe.
Not only would unaltered transistors draw more heat than is necesary, but it would be too easy to OC the cheapest chip to the same max speed. There is no advantage having the transistor reach saturation that much before the cycle ends.
As far as netburst goes, a northwood @ 3.6ghz using a 15.5 multiplier, would be able to handle A64. In other words, netburst isn't so much the problem, as how quickly it was implemented. I expect that a major part of Intel's planned new m-arch every two years, involves 4 or 5 more pipelines each time. Intel just failed to keep the pipes full enough.
As to SOI? Well, Houston, we have a problem. I believe that Intel should have implemented it. Sure, it would have cost a huge chunk of change, but it was wrong to leave the customer paying the extra heat premium. Why should the buyer be sponsoring stock options and Itanic R&D, if the company shows such utter disreguard for them?
Do I believe the new CEO will do things differently? The guy's a PR man, so I trust him as far as the proverbial toss.
May 2, 2006 5:11:41 AM

I think this might have been asked before, but how many cores can you theoretically place on one die?
May 3, 2006 2:08:51 AM

Quote:
I think this might have been asked before, but how many cores can you theoretically place on one die?


Picking up on JumpingJack's words (hope you don't mind, Jack) & giving a practical, actual example of a multi-core chip in a 90nm process: Sun UltraSPARC T1 (aka "Niagara").

Some general specs:

Architecture: SPARC V9;
Adress space: 48-bit virtual, 40-bit physically;
Cores: (up to) 8 cores running 4 threads each;
Pipelines: 8 integer units with 6 stages, 4 threads running on a single core share one pipeline;
Clock speed: 1.0 GHz - 1.2 GHz;
L1 Cache (per Core): 16 KByte instruction cache, 8 KB data cache (4-way set-associative);
L1-to-Core Bandwidth: 200GB/s;
L2 Cache-3 MByte on chip (shared), 12-way associative, 4 banks;
Memory Controler: four 144-bit DDR2-533 SDRAM interfaces; ~25.6GB/s
4 DIMMS per Controller - 16 DIMMS total;
Optional: 2-Channel operation mode;
JBUS Interface: 3.1 GByte/sec bandwidth (peak);
128 bit address/data bus, 150 - 200 MHz;
1 x FPU (shared);
Technology-CMOS, 90nm, 9-Layer Cu Metal;
Power Consumption: 72 - 79 Watt.


This is no gaming or multimedia beauty: This is a dedicated server task gobbling CMT (Chip Multi-Processing).
Each core is capable of issuing 4 threads simultaneously (4x8=32) & executing an average of 0.7 IPC per core.

Considering its unique uArch (damn! I hate this word!), with relatively small [shared] caches (750KB L2 per core!), a single shared FP unit and fairly simple cores, without Out-of-Order execution nor branch prediction units & with a single, 6-stage pipeline per core, a die-area of about 340mm^2 would seem an engineering real-estate mistake, at best. However, this eight-core chip's area doesn't even amount to the double of a dual-core Opteron, with a die-area of approx. 199mm^2, using the same 90nm process! And this, is quite an Engineering achievement!

Engineering, overall, is also about economy & management; I'd dare to say that these two aspects are really at the basic foundational principles of Engineering itself.
Apparently, utterly different microarchitectural approaches to computing seem to provide enough common ground to be compared (http://www.anandtech.com/printarticle.aspx?i=2657) and, in more than one way, give some perspective to the simplistic question «...how many cores can you theoretically place on one die?».

I'd answer that, despite the differences & the challenges, it depends on the engineering skills, actually.

Useful links:

http://en.wikipedia.org/wiki/UltraSPARC_T1;

http://www.rz.rwth-aachen.de/computing/hpc/hw/niagara.php;

http://www.sun.com/blueprints/1205/819-5144.pdf

...and a link to the team responsible for this processing marvell, the Afara Team: http://opensparc.sunsource.net/nonav/bios/profiles.html
(After all, we all know that there's more to it than Intel vs AMD, right?! :wink: )

Edit: Correction: Replaced «...issuing 32 threads...» with bold/underlined. My excuses. :oops: 



Cheers!
May 3, 2006 2:18:12 AM

Quote:
I think this might have been asked before, but how many cores can you theoretically place on one die?

.....This is no gaming or multimedia beauty: This is a dedicated server task gobbling CMT (Chip Multi-Processing).
Each core is capable of issuing 32 threads simultaneously & executing an average of 0.7 IPC per core. 8O
May 3, 2006 4:36:21 AM

Xenon/Waternoose is another. Triple-core with 1mb of L2 cache in 165m transistors. Shame it has no OOOe.
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