How does a multiway cache (2way, 8 way) work?

[chime]

In Anand Tech 's Core architecture vs. K8, it mentions the 2-way cache, 8-way cache. Can someone explain to me how it works or give me some pointers, please?

Thanks.

Chime :? :? :?

 

[accord99]

http://arstechnica.com/articles/paedia/cpu/caching.ars/5