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K8L sounds like a QC monster

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  • Quad Core
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Last response: in CPUs
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May 16, 2006 7:56:48 PM

Quote:
First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.

The first thing I really like is that K8l is in fact a native quad core design. The next thing i like is the C&Q taken to the next level. This is one of my favorite things about my 3700+. When it's idling it lowers the voltage to 1.1V and the clockspeeds to 1ghz. They will be able to do this x4 now and even shut off cores not in use. Imagine a QC chip that idles at less than 30watts on 65nm 8)
Quote:
Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

This is where the open HTT standard really shines for AMD because now they can officially drop in co-proc's for specific tasks which all-in-all makes the platform that much more flexible. I'm not sure what they mean by 1gig pages though and i'd rather get an explanation from Mr Potatoe Head, JJ or AM on this one.
Quote:
IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.


Quote:
The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

I think AMD's engineer's have been hanging out with the Isreal team because they seem to be on the same page these days :D 
BTW the title should be all caps i know but dont shoot the messenger. This all came from AMD and there is more info over there if u guys wnana check it out.
http://www.theinquirer.net/?article=31761
http://www.theinquirer.net/?article=30042

Some info i pulled from the [H]OCP forums which seems to point towards 2x 128bit SSE units rather than 2x64bit which the inq showed.
0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions

More about : k8l sounds monster

May 16, 2006 8:11:34 PM

K8MAN, You've beat me on this one. The difference in posting time is 3 minutes. Sorry I didn't saw your thread. Next time use caps. :D 
May 16, 2006 8:13:37 PM

Quote:
K8MAN, You've beat me on this one. The difference in posting time is 3 minutes. Sorry I didn't saw your thread. Next time use caps. :D 

I found it to be the most interesting news today although AMD's 65 and 35 watt chips are also looking nice.
Related resources
May 16, 2006 8:27:32 PM

Well. Inquirer garbage again.

Shared cache. Where have I seen it?
May 16, 2006 8:27:57 PM

Still, I'd like to contribute to your thread with this other source from The Register:
Quote:
AMD confirmed details of its "Next Generation Processor Technology" today, but it's really business as usual for the company. As AMD heads to four-core country, the company will continue to improve the bandwidth of its processor package, tweak memory and rely on help from partners to compete with an upcoming line of revamped chips from Intel.

Close AMD watchers will not be taken aback by any of the revelations made by senior fellow Chuck Moore today at the Processor Forum in San Jose. More than anything Moore just put an official stamp on what has been known for months.
The company still plans to deliver a four-core chip in 2007 and expects the product to compete well on overall performance and performance pet watt metrics. AMD pitches the no surprises approach as an advantage over Intel, which in the second half of this year will release a completely new processor architecture across its server, desktop and mobile lines. Even beyond that, Intel is expected to release more architectural changes in the coming years as it tries to improve memory performance.

The chips built with this design will have a few key changes over current products.

First off, AMD is touting a speedier version of HyperTransport that can handle 5.2 gigatransfers per second. The HyperTransport technology has proved key to AMD's performance edge over Intel. AMD expects more server makers to start shipping boxes with HTX slots that allow for add-on cards to slot into the HyperTransport framework, although companies such as Sun Microsystems continue to portray HTX as a niche play for the moment.

The second major change will be the presence of shared L3 caches in AMD's upcoming chips. AMD will continue to have "private L2 caches" but will add the on-chip L3 cache to improve overall performance.

"We believe this strikes the right balance," Moore said, during a speech. "This is a really interesting way to handle the memory hierarchy and it's in stark contrast to the brute force method (used by Intel)."

Intel has relied more and more on enormous caches to improve its chips, although the company seems to be moving away from that practice in future products.

AMD has also added better power management tools, so that a system can independently power the north bridge and CPU. In addition, future chips will have twice the floating point performance, support for 1GB memory pages, DDR2 and DDR3 (when it arrives) memory support, FB-DIMM memory support and improved RAS features such as memory mirroring and memory diagnostics.

Overall, AMD is concentrating on keeping single thread software performance high, while paving the way for more multithreaded applications. Moore urged the chip industry to provide "hooks" that can make designing multithreaded applications easier.

Today, AMD claims to enjoy up to a 95 per cent power consumption advantage over Intel. Even when Intel releases its new products, Moore claimed that AMD would still have a 43 per cent power consumption advantage, although apples to apples comparisons are close to impossible at the moment due to a lack of Intel product.

AMD expects more co-processors to start popping up for its chips in the coming years to help out with tasks such as Java, TCP/IP and SSL processing. The company's open specifications tend to make it easier for third parties to create products around AMD's gear than is the case for Intel, although Intel does enjoy a large partner network thanks to its massive market share.

Moore continued to knock Intel's dual-core and future four-core products as not being actual multicore gear for the most part. Intel has tended to create multi-core products by simply packaging numerous cores next to each other rather than building them into a single die.

AMD was able to secure a performance lead over Intel by arriving first to the 64-bit scene and then following that with dual-core products. The company, however, now seems to have run out rabbits to pull out of the hat. It's all about execution now, according to the little chipmaker that could.

http://www.theregister.co.uk/2006/05/16/amd_next_gen/

I still do believe AMD to come up with their own response to intel's SSE4.
May 16, 2006 8:41:13 PM

Quote:
Well. Inquirer garbage again.

Shared cache. Where have I seen it?

Its not like this is all from an AMD keynote or something :roll:
May 16, 2006 9:16:33 PM

2H2007 from AMD's......
Waiting Conroe sucessor.

ES please!!!!!
May 16, 2006 9:23:09 PM

All this means nothing until AMD shows me an engineering sample. Hell I have a manuscript on the planned future of octo-core, 6 ghz, 20 cycle, .01nm processor in me desk drawer, wow I guess I've got the biggest potential cock on the block, eat that Intel and AMD.
May 16, 2006 9:38:56 PM

Let me also join the K8L frenzy by posting this article: :D 
AMD unveils architecture for its next generation of chips

Quote:
Advanced Micro Devices will come out with a new chip architecture next year, and it's not messing with the basic formula that has helped it take market share away from Intel.

The new chip architecture--currently dubbed the Next Generation Processor Technology--enhances the design underlying the current Opteron, Turion and Athlon 64 chips. Performance will increase and AMD will keep a lid on power consumption, but the company has veered away from making radical conceptual changes in the overall blueprint. Processors built under the new design will come out in 2007.

"Rather than focus on coming out with a new core every other year, we're focusing on the big picture" of overall system performance, said Chuck Moore, a senior fellow at AMD.

Intel, by contrast, is overhauling the basic architecture of its chips in the second half of 2006 and will follow with more incremental design changes in subsequent years. The company asserts that processors based on the architecture--Merom, Conroe and Woodcrest, will substantially outdo contemporary AMD chips by 20 percent and reduce power consumption.

While Moore didn't make a point-for-point comparison with Intel's future chips, he asserted that right now AMD is beating the company he called AMD's nearest competitor.

"When you compare the performance and power consumption, there is an enormous difference," he said.

Which company comes out with the superior chip architecture over the next 18 months will be one of the big issues in the PC market in 2007 and will ultimately depend on a host of factors.

Chips built under the new AMD architecture will feature a faster version of HyperTransport, an input-output technology featured on AMD chips. HyperTransport 3.0, recently approved by the standards body that governs the development of the technology, will accomplish 5.2 gigatransfers (5.2 billion transfers of data) per second, Moore said. Although it doesn't get as much attention as 64-bit processing, HyperTransport is behind much of the performance gains of AMD chips in recent years.

The new chips will also sport four processing cores. AMD's best chips currently come with two processing cores.

One of the biggest changes will come in the caches, reservoirs of memory built into the processor for rapid data access. In current AMD chips, each core has two caches and those caches are completely dedicated to their respective cores. In future chips, each core will also have two dedicated caches, but the cores will also share a third cache. With the third cache, the processor will less often have to fetch data from main memory--a time-consuming process.

Intel chips typically have larger caches. Intel, however, does not integrate a memory controller onto its chips like AMD does. This also cuts down memory latency. Whether it's better to have a larger cache and a separate memory controller or a smaller cache with an integrated memory controller is the source of an ongoing debate between the two companies.

The upcoming AMD chips will also curb power consumption by allowing the memory controller or the processor core to independently power down during idle periods, Moore said. The memory controller and processing cores currently slow down during slow periods, but only when both are relatively idle.

The integrated memory controller on the new chips will also connect to DDR2 memory and accommodate DDR3, a memory specification under construction, at the appropriate time, Moore added. Intel will match its future server chips with another memory standard, called FB-DIMM. Again, which of these is better is under debate between the two companies. AMD says that FB-DIMM produces more heat.

An Intel representative said the amount of extra energy is minimal, adding that AMD won't support FB-DIMM faster than standard DDR memory because of the integrated memory controller.

Moore outlined AMD's plans at the Spring Processor Forum in San Jose, Calif.
a b à CPUs
May 16, 2006 9:54:41 PM

hmmmzzz

when intel says specs we all poo hoo *shrugs*

and its from the inquirer - why wasnt i suprised.

MORE TO THE POINT quad core on intels FSB might give AMD here an advantage instantly reguardless of core tweaks - until something like CSI actually comes out, perhaps intels next target.

Quote:
First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.

The first thing I really like is that K8l is in fact a native quad core design. The next thing i like is the C&Q taken to the next level. This is one of my favorite things about my 3700+. When it's idling it lowers the voltage to 1.1V and the clockspeeds to 1ghz. They will be able to do this x4 now and even shut off cores not in use. Imagine a QC chip that idles at less than 30watts on 65nm 8)
Quote:
Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

This is where the open HTT standard really shines for AMD because now they can officially drop in co-proc's for specific tasks which all-in-all makes the platform that much more flexible. I'm not sure what they mean by 1gig pages though and i'd rather get an explanation from Mr Potatoe Head, JJ or AM on this one.
Quote:
IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.


Quote:
The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

I think AMD's engineer's have been hanging out with the Isreal team because they seem to be on the same page these days :D 
BTW the title should be all caps i know but dont shoot the messenger. This all came from AMD and there is more info over there if u guys wnana check it out.
http://www.theinquirer.net/?article=31761
http://www.theinquirer.net/?article=30042

Some info i pulled from the [H]OCP forums which seems to point towards 2x 128bit SSE units rather than 2x64bit which the inq showed.
0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions
May 16, 2006 11:12:57 PM

I feel real good now because they did exactly what I said they would. It's good to be the King.
May 16, 2006 11:27:20 PM

Quote:
First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.

The first thing I really like is that K8l is in fact a native quad core design. The next thing i like is the C&Q taken to the next level. This is one of my favorite things about my 3700+. When it's idling it lowers the voltage to 1.1V and the clockspeeds to 1ghz. They will be able to do this x4 now and even shut off cores not in use. Imagine a QC chip that idles at less than 30watts on 65nm 8)
Quote:
Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

This is where the open HTT standard really shines for AMD because now they can officially drop in co-proc's for specific tasks which all-in-all makes the platform that much more flexible. I'm not sure what they mean by 1gig pages though and i'd rather get an explanation from Mr Potatoe Head, JJ or AM on this one.
Quote:
IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.


Quote:
The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

I think AMD's engineer's have been hanging out with the Isreal team because they seem to be on the same page these days :D 
BTW the title should be all caps i know but dont shoot the messenger. This all came from AMD and there is more info over there if u guys wnana check it out.
http://www.theinquirer.net/?article=31761
http://www.theinquirer.net/?article=30042

Some info i pulled from the [H]OCP forums which seems to point towards 2x 128bit SSE units rather than 2x64bit which the inq showed.
0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions

Change Northbridge voltages independently of the cores?

Could be one gig page file per core or one gig software footprint per core, either or 2 gig's is what 32bit machines barriers are sounds to me if this information is correct they are essentially taking a step backward.

But it’s the inquirer so I will take it with a grain of salt.
May 16, 2006 11:31:36 PM

Quote:
Well. Inquirer garbage again.

Shared cache. Where have I seen it?

Its not like this is all from an AMD keynote or something :roll:

This is from the Spring Proc Forum. Directly from AMD. It means they MAY get 6 IPC out of K8L. If so, Conroe is dusted off.
May 16, 2006 11:34:19 PM

Quote:
Well. Inquirer garbage again.

Shared cache. Where have I seen it?

Its not like this is all from an AMD keynote or something :roll:

This is from the Spring Proc Forum. Directly from AMD. It means they MAY get 6 IPC out of K8L. If so, Conroe is dusted off.

Right...
May 16, 2006 11:36:16 PM

He's the king of talking about things he has no idea about.
May 16, 2006 11:39:12 PM

Quote:
I feel real good now because they did exactly what I said they would. It's good to be the King.
Ya you said it now wheres that apology from Action_man?
May 16, 2006 11:40:19 PM

Quote:
He's the king of talking about things he has no idea about.


Word.
May 16, 2006 11:42:00 PM

It's nice to see the rettihSlluB and 9-inch are both back again.

Quote:
Some info i pulled from the [H]OCP forums which seems to point towards 2x 128bit SSE units rather than 2x64bit which the inq showed.

I was just wondering what you meant by that. My interpretation was that this relates to the statements about doubled FPUs in other words the 2 existing FPUs + 2 new 128bit SSE units. I'm assuming they'll add another FStore while they're at it to bring the total to 6 FP/SSE related units.

It's been mentioned many times, but hopefully AMD will expanded the L1 bus from 128bit to 256bit to improve bandwidth. Increasing the associativity of the L1 cache from 2-way to 4-way will also help improve hit rates.

In any case, I think The Register article that 9-inch posted is most relevent.

Quote:
AMD was able to secure a performance lead over Intel by arriving first to the 64-bit scene and then following that with dual-core products. The company, however, now seems to have run out rabbits to pull out of the hat. It's all about execution now, according to the little chipmaker that could.

What I'd like to know is clarification of when K8L will really be released and in what products. According to roadmaps that 9-inch recently posted, the first quad core won't arrive until H2 2007 and Deerhound doesn't include a shared L3 cache, FB-DIMM support or Hypertransport 3.0. I haven't heard when K8L will make it's way to desktop chips since AMD hasn't given any indication that the 65nm chips they plan on shipping in December will be based on the new microarchitecture. Those are going to run at the same clock speeds as Rev F Windsor chips and use the same name so they look to be simply die shrinks.
May 16, 2006 11:43:14 PM

K8man you are the most intelligent amd fanboy here keep up the good work. :D 
May 17, 2006 12:00:21 AM

Quote:
First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.

The first thing I really like is that K8l is in fact a native quad core design. The next thing i like is the C&Q taken to the next level. This is one of my favorite things about my 3700+. When it's idling it lowers the voltage to 1.1V and the clockspeeds to 1ghz. They will be able to do this x4 now and even shut off cores not in use. Imagine a QC chip that idles at less than 30watts on 65nm 8)
Quote:
Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

This is where the open HTT standard really shines for AMD because now they can officially drop in co-proc's for specific tasks which all-in-all makes the platform that much more flexible. I'm not sure what they mean by 1gig pages though and i'd rather get an explanation from Mr Potatoe Head, JJ or AM on this one.
Quote:
IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.


Quote:
The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

I think AMD's engineer's have been hanging out with the Isreal team because they seem to be on the same page these days :D 
BTW the title should be all caps i know but dont shoot the messenger. This all came from AMD and there is more info over there if u guys wnana check it out.
http://www.theinquirer.net/?article=31761
http://www.theinquirer.net/?article=30042

Some info i pulled from the [H]OCP forums which seems to point towards 2x 128bit SSE units rather than 2x64bit which the inq showed.
0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions

Change Northbridge voltages independently of the cores?

Could be one gig page file per core or one gig software footprint per core, either or 2 gig's is what 32bit machines barriers are sounds to me if this information is correct they are essentially taking a step backward.

But it’s the inquirer so I will take it with a grain of salt.


What it actually means is that if you have 2GB RAM it will be held in two pages (it's gives a flatter memory space) rather than 4 or more. As far as the voltage, that is a great feat. It means that there are 4 regulators with a HW ctrlr with hooks into C&Q. Turning off 3 cores will be great for workstations and cluster nodes. Add the nVidia "Tritium" stuff and K8L will be killer. I'm just surprised they don't add the new prefetch and wider SSE to AM2. But then by the time Conroe really makes a splash, K8L will be out. I think they should add the other improvements to dual core too, though. I mean, I don't even REALLY need quad core yet and I run VM sessions and Visual Studio.
May 17, 2006 12:03:08 AM

Quote:
He's the king of talking about things he has no idea about.


Word.

May 17, 2006 12:17:03 AM

Action Man.... Give him his rightful place.
King of the Hill!!! To be more specific. BullShit Hill...
May 17, 2006 12:18:58 AM

Quote:
First, it has a shared expandable L3 cache, necessary because it is a native quad-core design. The one massive enhancement to the mix is that AMD finally has the ability to independently change core voltages for power savings. It now can also change the north bridge voltage independently of the cores. This is a huge win, we are told voltage differentials and problems with them were one of the main scaling headaches of the K8 core to this point.

The first thing I really like is that K8l is in fact a native quad core design. The next thing i like is the C&Q taken to the next level. This is one of my favorite things about my 3700+. When it's idling it lowers the voltage to 1.1V and the clockspeeds to 1ghz. They will be able to do this x4 now and even shut off cores not in use. Imagine a QC chip that idles at less than 30watts on 65nm 8)
Quote:
Next is memory. The new core will support 48-bit addressing and 1GB pages. Cray and SGI will be very happy with this, until they hit that memory wall again. There is also official co-processor support, strongly hinted to be on a HTX card. The key here will be the platform is aware of them vs having to hack them in.

This is where the open HTT standard really shines for AMD because now they can officially drop in co-proc's for specific tasks which all-in-all makes the platform that much more flexible. I'm not sure what they mean by 1gig pages though and i'd rather get an explanation from Mr Potatoe Head, JJ or AM on this one.
Quote:
IPC is also going up in a big way. It is doing the obvious doubling of SSE/FP resources, old news now, but it goes a lot deeper than that. There are a bunch of added instructions, starting with the bit manipulation instructions LZCNT and POPCNT. It also added SSE extensions EXTRQ/INSERTQ and MOVNTSD/MOVNTSS. No word on SSE4 though.


Quote:
The last bit is much more aggressive prefetch to 'feed the beast'. It has gone from 16B to 32B, an obvious step with the added SSE number crunching power. On top of this, it has out of order loads, and other tweaks to use the available bandwidth in a much more efficient manner.

I think AMD's engineer's have been hanging out with the Isreal team because they seem to be on the same page these days :D 
BTW the title should be all caps i know but dont shoot the messenger. This all came from AMD and there is more info over there if u guys wnana check it out.
http://www.theinquirer.net/?article=31761
http://www.theinquirer.net/?article=30042

Some info i pulled from the [H]OCP forums which seems to point towards 2x 128bit SSE units rather than 2x64bit which the inq showed.
0. Native quad core
1. Hypertransport up to 5.2GT/s
2. Better coherency
3. Private L2, shared L3 cache that scales up.
4. Separate power planes and pstates for north bridge and CPU
5. 128b FPUs - see 14,15
6. 48b virtual/physical addressing and 1GB pages
7. Support for DDR2, eventually DDR3
8. Support for FBD1 and 2 eventually
9. I/O virtualization and nested page tables
10. Memory mirroring, data poisoning, HT retry protocol support
11. 32B instead of 16B ifetch
12. Indirect branch predictors
13. OOO load execution - similar to memory disambiguation
14. 2x 128b SSE units
15. 2x 128b SSE LDs/cycle
16. Several new instructions

Change Northbridge voltages independently of the cores?

Could be one gig page file per core or one gig software footprint per core, either or 2 gig's is what 32bit machines barriers are sounds to me if this information is correct they are essentially taking a step backward.

But it’s the inquirer so I will take it with a grain of salt.


What it actually means is that if you have 2GB RAM it will be held in two pages (it's gives a flatter memory space) rather than 4 or more. As far as the voltage, that is a great feat. It means that there are 4 regulators with a HW ctrlr with hooks into C&Q. Turning off 3 cores will be great for workstations and cluster nodes. Add the nVidia "Tritium" stuff and K8L will be killer. I'm just surprised they don't add the new prefetch and wider SSE to AM2. But then by the time Conroe really makes a splash, K8L will be out. I think they should add the other improvements to dual core too, though. I mean, I don't even REALLY need quad core yet and I run VM sessions and Visual Studio.

Maybe I wasn't clear enough since when did the K8 have a Northbridge? The move to 64bit was to increase page allocation (footprint) from 2 gig to anything of choice within 4 terabytes. I don't see this as a forward direction for the technology.
May 17, 2006 12:19:32 AM

All of that info is coming from AMD. It hasnt been doctored or anything like that by the inq.
May 17, 2006 12:19:52 AM

Quote:
Well. Inquirer garbage again.

Shared cache. Where have I seen it?

Its not like this is all from an AMD keynote or something :roll:

This is from the Spring Proc Forum. Directly from AMD. It means they MAY get 6 IPC out of K8L. If so, Conroe is dusted off.

Right...


It figures the pnut gallery would be out. Are you threatened by me or something? Or do you and ActionMan come up with one-liners post-coitally?


I mean are you saying they can't get 6 IPC out of widening the registers or are you saying that it won't be fatser than Conroe's 4 IPC?
May 17, 2006 12:24:25 AM

Quote:
All of that info is coming from AMD. It hasnt been doctored or anything like that by the inq.
Well man keep up the good work.
May 17, 2006 12:28:27 AM

Quote:
Well. Inquirer garbage again.

Shared cache. Where have I seen it?

Its not like this is all from an AMD keynote or something :roll:

This is from the Spring Proc Forum. Directly from AMD. It means they MAY get 6 IPC out of K8L. If so, Conroe is dusted off.

Right...


It figures the pnut gallery would be out. Are you threatened by me or something? Or do you and ActionMan come up with one-liners post-coitally?


I mean are you saying they can't get 6 IPC out of widening the registers or are you saying that it won't be fatser than Conroe's 4 IPC?

6 IPC is absurd, that’s all I was commenting on. Threatened? I will have to admit that’s rich, but this is a forum why on earth would I be threatened. ActionMan and I aren't in collaboration to sully your good name.

I am saying AMD would need significantly more time to design a core to push 6 IPC this revision is a patch job (if you will) to the K8 to make it a bit more competitive and from what I am seeing it will only be in quad-core setups. Widening the registers sadly won’t give them an increase in IPC they will need to add additional decoders at this point.
May 17, 2006 12:32:38 AM

Quote:
Maybe I wasn't clear enough since when did the K8 have a Northbridge? The move to 64bit was to increase page allocation (footprint) from 2 gig to anything of choice within 4 terabytes. I don't see this as a forward direction for the technology.



Nothing I said mentioned north bridges. You are confusing addressing with paging. Addressing doesn't have to be 64 bit if the processor is. Paging is what Windows uses to allocate memory for processes. If you have a 1 GB page you can load a contiguous block of 1GB. It gives a greater increase than increasing from 1MB cache to 4MB cache for processes that use that much RAM - hence why they mentioned Cray and Sun.
May 17, 2006 12:43:58 AM

Quote:
Well. Inquirer garbage again.

Shared cache. Where have I seen it?

Its not like this is all from an AMD keynote or something :roll:

This is from the Spring Proc Forum. Directly from AMD. It means they MAY get 6 IPC out of K8L. If so, Conroe is dusted off.

Right...


It figures the pnut gallery would be out. Are you threatened by me or something? Or do you and ActionMan come up with one-liners post-coitally?


I mean are you saying they can't get 6 IPC out of widening the registers or are you saying that it won't be fatser than Conroe's 4 IPC?

6 IPC is absurd, that’s all I was commenting on. Threatened? I will have to admit that’s rich, but this is a forum why on earth would I be threatened. ActionMan and I aren't in collaboration to sully your good name.

I am saying AMD would need significantly more time to design a core to push 6 IPC this revision is a patch job (if you will) to the K8 to make it a bit more competitive and from what I am seeing it will only be in quad-core setups. Widening the registers sadly won’t give them an increase in IPC they will need to add additional decoders at this point.


Was it so hard to say that the first time? Even if they don't get 4 IPC out of the changes, it will still give them the advantage. They have 3 complex decoders at this point but if cycles take a shorter time with prefetch and out of order optimization, even without adding additional decoders, pipeline efficiency can be increased so that if IPC doesn't go up more work can be done per second with the decoders because they are receiving instructions faster from L1. I guess that would be moreso considered IPS.

Excuse me.
May 17, 2006 12:53:38 AM

the only real gain in K8L that will make a noticeable difference is the increase in FPU and Intel has that intigrated in the SIMD within the processor. So it wouldnt make any sence to add more FPU but intel added more ALU.

AMD doesnt have a chance with K8, its a dead architecture now until K10. K8L is a way for people like you and AMD to graps at straws. But we cannot just judge becasue of 1 damn forum post and 1 damn inquier post wich is alwasy about bs cause they claimed dell was going with AMD when we never see it.

So wait you damn fanboys, wait and see true benchies. I bet a lot of you, and I mean A LOT will just jump the ship to watever side. I know I will. Ive been too long with AMD but now, Intel will be my fav again, since its conroe will be a monster and dominate for market for a good couple of years until AMD comes out with something, then vice versa (the great life of technology)
May 17, 2006 12:59:28 AM

With K8L shooting for 6 IPC it will prove once more the fact that AMD's next marchitecture will double this number thanks to a 12-issue design and the help of the TRIPS architecture.
I also like K8L's die shot. Looks sexy.
May 17, 2006 1:40:26 AM

Nice article, I enjoy it as much as the HORDE. Finaly, some usefull info about AMD next-gen chips. This new QC will kick Clovertown's ass.
May 17, 2006 1:48:15 AM

I wonder if K8L is project M2 or as spud said, simply a rework. M2 is supposed to be magic as it has what AMD has been working on for at least 3 years. Conroe is a rework of an existing design and look how freaking fast that thing is gonna be. I mean they are making it work with the 865 chipset :lol: 
I'm not a profit but dont count AMD out as they have already stated that they can get quad core and K8L out the door this year if they really needed to. Not so far fetched as that picture looks like a taped out chip to me. They are already doing small run's of 65nm chips for testing and could launch 65nm with the same success as Intel. Either way just looking the situation with an open mind and the mindset that Intel might as well of already launched Conroe and now we are waiting for AMD with anticipation.
May 17, 2006 2:07:01 AM

It is a SERIOUS REWORK. Every part of the core is getting updated with more efficient and/or wider components. I can't believe they won't put this on the dual core. The desktop is not ready for quad yet.
May 17, 2006 4:05:24 AM

Quote:
Being able to simply make the CPU smaller - from 2 inches down to 1.2" - helps significantly, coupled with staying within a 28 to 35 watt consumption envelope. But in the desktop space, the power consumption equation starts to get significantly fuzzy. "By the time you put in one, two, three of these 150-watt graphics cards," Tuhy said, "you're literally talking about issues of power out of the wall. Some of these systems have two AC power cords coming out the back of them, to be able to draw from their dual power supplies.


This is from the Intel article just recently posted. Now I have not determined whether or not when they mention 28 to 35 watt envelope that they are talking about the current incarnation of the Conroe, however, it seems there is as much talk about it at Intel as there is at AMD.
May 17, 2006 6:39:14 AM

Quote:
It is a SERIOUS REWORK. Every part of the core is getting updated with more efficient and/or wider components. I can't believe they won't put this on the dual core. The desktop is not ready for quad yet.

The rework is doubling on the all K8 resources. No fundamental changegs and new stuff added(like micro¯oOP fussion, SMA), but they will achieve the goal, make faster CPU, no matter of the yields and production cost(or their price on the market). Those K8L chips are reserved for the server arena, they goes to SocketF.
Anyway, the desktop is ready for everything, but the software is not ready for the quad, nither for teh dual core and 64bit CPUs.
May 17, 2006 8:18:42 AM

Well I may be new to this but I have to agree with gOJDO when he said,
Quote:
.....but the software is not ready for the quad, nither for the dual core and 64bit CPUs.

The majority of software out their is not ready for 64-bit let alone Dual-core, Quad-core Ha. I'm all for progress but I think that were getting ahead of our selves, but hey nothing we can do about it except go with it.
May 17, 2006 8:53:02 AM

Quad core really is more for servers than desktop.
I would think there are a few companies out there that would like to get thier hands on a 32 core server, at a price premium of "only $8000" over an 8 chip setup.
May 17, 2006 9:14:35 AM

Adding another FPU and widening SSE to 128 bit will impact IPC.
As to 6 IPC, well that seems absurd since a 12 stage pipe sees about 10 wait states per output.
May 17, 2006 9:46:57 AM

A bigger point would be AMD's efficiency with SIMD extensions. If they can't get SSE to work better, 128 bit wont do much. On the other hand. if they do get it right this time, 10% might be very low.
May 17, 2006 9:49:38 AM

I found this pic on the net which has a comparisson of AMD's future quad core vs dual core:



Did you guys noticed the added FP unit?? 8)
May 17, 2006 10:15:07 AM

They were thinking about the more issue superscallar cores efficiency. The better branch prediction, the OoO load execution, the double of the SSE load/store units and the shared L3 cache. The K8L is designed for multitasking server environment. There will be use of the extra execution units.
May 17, 2006 7:42:32 PM

Looks like Socket F (K8L's upcoming socket) will see the light of day in july:

Quote:
THE TIME OF Rev. F is approaching rapidly. Since Intel used the last two weeks to invite highly-ranked journalists to test WoodCrest processors in a secret bunker in Oregon, AMD hasn't been sleeping lightly.
The performance level of WoodCrest may be putting the smiles back on the faces of Intellers, but those smiles tend to disappear when you mention four or eight-socket platforms. WoodCrest has a ticket to ride in the single and dual-socket arena, but anything more than that ends in tears and bottlenecked system bus, which just can't keep up with coherent HyperTransport links in-between the cores.

AMD's first-hand response was the briefing on the impressive K8L architecture, which our own Charlie has thoroughly dissected over the past couple of months. The DDR-II 400/533/667/800 supporting, 1207-golden dot processor is scheduled to debut in the coming weeks.

New packaging puts it on the same level as Intel and, of course, we're talking about the Land Grid Array packaging. The New Opterons bring several improvements to the table, with the most notable one being an improved memory controller. The purpose of new memory controller is solving that nasty 1GB/s read and write speed lag that company experienced when it introduced dual-cores to the product line.

We heard that the platform will be out the door with all the supporting products on 11th of July, but you can expect a lot more info at Computex, a month ahead of the official introduction. Intel had a lot of Conroes Core 2 Duos shown at the E3 show, a month ahead of the official launch.

Of course, you can expect our detailed coverage from Computex, which is scheduled to open on June the 6th, just a mere three weeks from now.


http://www.theinquirer.net/?article=31787
May 17, 2006 7:52:04 PM

Quote:
The first thing I really like is that K8l is in fact a native quad core design.


While I love to have a quad core CPU (I'm a 3D rendering junkie), most users around the world won't see a damn difference unless somehow AMD/Intel gets single-threaded apps to parallelize themselves across the separate cores ala Hyperthreading but better. I know AMD/Intel have researched this. I feel it is more important than quad, octo, etc. designs.

I highly doubt software will change for the sake of hardware - witness Itanium (I love bashing it). Apps will remain single-threaded for a while to come and compilers/languages aren't smart enough to parallelize code well (in fact they usually suck at it).
May 17, 2006 9:37:22 PM

what AMD has to beat a conroe??? can't tolerate if AMD lose the ground again...
May 17, 2006 9:54:43 PM

LOLS. Don't worry your crazy little head "islam-man-jurul" Remember the saying "There's always Dead Quite(silence), before the Hurricane" So althoguh AM2 might be a flat baloon and the AM2 Procs FX-62 and AMD ATHLON64 5000+,5200+ seem like overclocked versions of their older brothers, AMD has 65nm comming and K8L that revised and reviewed K8 core comming along with threats from AMD to INTEL that they have an answer to CONROE and MEMROM. And the news from AMD that they have 35W and 65W dual core on the works. SO no point worrying about AMD because they are just releasing AM2 and sitting tight to conjure up the Hurricane season for next year ( you guys from Mississippi, Louisiana and Florida) *hurricanes do kill, hurt and destroy.
May 17, 2006 10:27:46 PM

well i m aware of all these facts, but my question is if AMD is late, as seen on their roadmap then how it will survive??? a good processor doesn't mean everything is good, but a good market do mean it, which intel has, and may be will expand after conroe... so how to beat intel's market policy..... AMD need to do that badly....
May 17, 2006 10:46:42 PM

Intel still cant compete in the 4-8way space(and beyond) with what AMD has coming out later this year and even some of the high-end stuff shipping right now. They know they are not gonna compete on the desktop for a few months so they are giving all the good stuff to the server industry until they come back with more single threaded performance.
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