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Can someone tell me the advantages and disadvantages of IMC?

Last response: in CPUs
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June 7, 2006 2:54:04 PM

I've been trying to research integrated memory controller. but most of the sites i found tend to be a little AMD-biased. can someone please find some sites that explains the integrated memory controller? if you know anything, please post replies as well. thank you.
June 7, 2006 3:18:38 PM

THe PS3 Cell CPU uses an integrated memory controller. You could search the R&D papers for why they chose IMC - probably for high-memory bandwidth. The 6-7 subprocessors inside the Cell don't have an L2 cache and don't do OoOe/Out-of-order execution (neither does Itanium I think). It's a very "radical" design.
June 7, 2006 8:04:47 PM

Quote:
I've been trying to research integrated memory controller. but most of the sites i found tend to be a little AMD-biased. can someone please find some sites that explains the integrated memory controller? if you know anything, please post replies as well. thank you.



I'm not sure if you mean the pros/cons of an IMC, or the actual architectual design of it. The IMC is a relatively simple concept in theory - it's basically moving part of the Northbridge onto the actual chip die to deal with memory access. AMD's implementation is a bit more complex because of their multiple HTT links.

Here's a brief rundown of the pros/cons, if this is what you wanted (since you were talking about the AMD site bias).

Pros:

[*:c6d0d568c6]Lower latancies (no need to go to Northbridge for memory access - essentially skipping a step)
[*:c6d0d568c6]Usually results in higher theoretical memory bandwidth (but not necessarily)
[*:c6d0d568c6]With AMD's HTT, multiple sockets scale much better than a shared-FSB design.
[*:c6d0d568c6]Generally lower chipset cost and power requirements (due to reduced cost/complexity of Northbridge components)


Cons:

[*:c6d0d568c6]Lack of flexibility in new memory types. AMD has to redesign the IMC in their chip with each new memory technology.
[*:c6d0d568c6]Takes of precious logic die space. (Cache is less likely to have critical defects than logic)
[*:c6d0d568c6]Can increase chip power usage (due to the afformentioned point)
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