Interesting rumour for AM2 and inverse threading

http://www.xtremesystems.org/forums/showthread.php?t=103636

This isnt official but the general consensus is that it is true and there is some kind of virtualization built into AM2 chips that just needs a BIOS update so activate and it's coming after Conroe. Would be very interesting if this was true.
Discuss
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More about interesting rumour inverse threading
  1. Indeed it would be something if true...
    But link indicated this info comes from a well know Russian site which spreads FUD... :roll:
  2. Maybe the single virtual core will have the hyperthreading trick that AMD gave the original X2 line so that HT optimized apps would run well on X2 so when there are more threads than one It splits the load up again into 2(or more) threads. It may seem silly but i dont think they can have the OS switch between 1 and 2 core mode on the fly. Who know's though I guess we'll have to wait for answers.
  3. Quote:
    Maybe the single virtual core will have the hyperthreading trick that AMD gave the original X2 line so that HT optimized apps would run well on X2 so when there are more threads than one It splits the load up again into 2(or more) threads. It may seem silly but i dont think they can have the OS switch between 1 and 2 core mode on the fly. Who know's though I guess we'll have to wait for answers.


    Problem is it isn’t going to be a virtual core, which is the underlying principal of Hyper Threading. Also AMD X2 core set up, accesses XP's 2 physical core code base not XP's Hyper Threading code base or XP's single core code base.

    As per the OS switching from 1 to 2 threads on the fly is very much impossible at this point, future OS development might bring something like that to light but I highly doubt it since the compiler makes the final say on threads.

    As far as I am concerned at this point AMD is blowing more white smoke to pawn off something that the OS manages anyways. Why take 1 thread spit it into 2 and work on it at the same time, oh wait that is already being done on current dual core, HT, and dual processor environments. They are pulling more crap to undermine the Core 2 Duo launch, the only problem is the fundamental technology they are trying to pawn off as new already exists and has been around for quite some time.
  4. Quote:
    Maybe the single virtual core will have the hyperthreading trick that AMD gave the original X2 line so that HT optimized apps would run well on X2 so when there are more threads than one It splits the load up again into 2(or more) threads. It may seem silly but i dont think they can have the OS switch between 1 and 2 core mode on the fly. Who know's though I guess we'll have to wait for answers.


    Problem is it isn’t going to be a virtual core, which is the underlying principal of Hyper Threading. Also AMD X2 core set up, accesses XP's 2 physical core code base not XP's Hyper Threading code base or XP's single core code base.

    As per the OS switching from 1 to 2 threads on the fly is very much impossible at this point, future OS development might bring something like that to light but I highly doubt it since the compiler makes the final say on threads.

    As far as I am concerned at this point AMD is blowing more white smoke to pawn off something that the OS manages anyways. Why take 1 thread spit it into 2 and work on it at the same time, oh wait that is already being done on current dual core, HT, and dual processor environments. They are pulling more crap to undermine the Core 2 Duo launch, the only problem is the fundamental technology they are trying to pawn off as new already exists and has been around for quite some time.

    Word.
  5. Quote:
    As far as I am concerned at this point AMD is blowing more white smoke to pawn off something that the OS manages anyways. Why take 1 thread spit it into 2 and work on it at the same time, oh wait that is already being done on current dual core, HT, and dual processor environments. They are pulling more crap to undermine the Core 2 Duo launch, the only problem is the fundamental technology they are trying to pawn off as new already exists and has been around for quite some time.


    Wonder where they would ever get that idea :roll:
    Oh and btw AMD isnt touting this. It's a secret.
  6. They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:
  7. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:
    Maybe if you were'nt so bias. You know what Ycon nevermind there's no point in argueing with an intel fanboy of your calibur you've been brainwashed beyond belief even the mention of a company that is a rival to intel and the only thought's that come into your brain are Not...intel...bad...must...say...bad things! Geez dude stop trashing amd at every turn they had their turn in the spotlight and now intel's got their's. Do i trash conroe all the time? No! Cause i know it's gonna be good what if amd pull's out a rabbit from their ass like they did with k8? And let's say that this new architecture has a 10% performance increase over conroe? What would you do then huh? Would you still trash amd knowing that they are better or would you admit defeat and get along with the rest of us here?
  8. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:


    It's an inovation that could unify the quest for parrallelism with the quest for single threaded performance. Whats wrong with that? If it's working already then all they need to do is add more core's and then devise a system to keep those cores fed. It would be like the string theory of the CPU world where everything is based off of a simple design which can be infinitly expanded. :wink:
  9. I trully doubt AMD would release this "technology" this year, (IF EVER) lol

    From a development standpoint i think it sucks, i dont' want 2 cpu's to act as one, please no more SLI wet dreams lol

    I want to work on numerous software applications at the same time, all this gives you is a SLI based dual CORE cpu, which time slices the threads/proccesses running on it no doubt :lol:

    So yeah it would be fast, but it wouldn't solve problems with 12 intensive apps running at the same time, and one behaving like a pig and hogging CPU time.
  10. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:


    It's an inovation that could unify the quest for parrallelism with the quest for single threaded performance. Whats wrong with that? If it's working already then all they need to do is add more core's and then devise a system to keep those cores fed. It would be like the string theory of the CPU world where everything is based off of a simple design which can be infinitly expanded. :wink:

    The quest for parallism has already come and gone, modern day compilers do a fantastic job of it already. As well current implementations of SPARC, MIPS, Cell, Itanium or anything RISC does a fantastic job at parallel execution. But that’s a single die execution environment, changing the page to dual core or higher adds significant code complexity roughly every core would add 125% more coding/debug time as well with the current limitations imposed by x86 machines; shifting, page access, memory allocation, branching, looping, pointer limitations, register renaming, instruction order limitations, vectorizeing limitations, stack size limitations, memory segmentation limits, array sizes, and the lack there of 32bit and 64bit registers. Hinder that progress of efficient code execution.

    As per single threaded performance we are starting to see the single thread performance slowing and normalizing, while dual and quad have promising thread performance, much of that that performance will be from the code base and compiler used. This currently looks to be already established in key development and media apps, but won’t likely ever make its way into the general computing environments as some would hope. Unless the software industry decided to have a performance war, which isn’t going to happen, because KISS rules all.

    But that’s not saying GCC or ICC compilers couldn’t create the binary for such adventitious endeavors. But even with the compilers and decent coding you will still need a very robust hardware configuration.

    Oh and the String theory doesn’t work since we are all running OOO machines.
  11. You can tell its fake once they mention that MS will release a patch for it.
  12. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:
    Maybe if you were'nt so bias. You know what Ycon nevermind there's no point in argueing with an intel fanboy of your calibur you've been brainwashed beyond belief even the mention of a company that is a rival to intel and the only thought's that come into your brain are Not...intel...bad...must...say...bad things! Geez dude stop trashing amd at every turn they had their turn in the spotlight and now intel's got their's. Do i trash conroe all the time? No! Cause i know it's gonna be good what if amd pull's out a rabbit from their ass like they did with k8? And let's say that this new architecture has a 10% performance increase over conroe? What would you do then huh? Would you still trash amd knowing that they are better or would you admit defeat and get along with the rest of us here?

    Splinter. Plank. Eye.

    Add some extra words and the concept should become clear.
  13. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:


    It's an inovation that could unify the quest for parrallelism with the quest for single threaded performance. Whats wrong with that? If it's working already then all they need to do is add more core's and then devise a system to keep those cores fed. It would be like the string theory of the CPU world where everything is based off of a simple design which can be infinitly expanded. :wink:

    The quest for parallism has already come and gone, modern day compilers do a fantastic job of it already. As well current implementations of SPARC, MIPS, Cell, Itanium or anything RISC does a fantastic job at parallel execution. But that’s a single die execution environment, changing the page to dual core or higher adds significant code complexity roughly every core would add 125% more coding/debug time as well with the current limitations imposed by x86 machines; shifting, page access, memory allocation, branching, looping, pointer limitations, register renaming, instruction order limitations, vectorizeing limitations, stack size limitations, memory segmentation limits, array sizes, and the lack there of 32bit and 64bit registers. Hinder that progress of efficient code execution.

    As per single threaded performance we are starting to see the single thread performance slowing and normalizing, while dual and quad have promising thread performance, much of that that performance will be from the code base and compiler used. This currently looks to be already established in key development and media apps, but won’t likely ever make its way into the general computing environments as some would hope. Unless the software industry decided to have a performance war, which isn’t going to happen, because KISS rules all.

    But that’s not saying GCC or ICC compilers couldn’t create the binary for such adventitious endeavors. But even with the compilers and decent coding you will still need a very robust hardware configuration.

    Oh and the String theory doesn’t work since we are all running OOO machines.
    Once again AMD has been working on this since K8 first hit market so they've had alot of time and probably have a lot invested into this tech. My string theory comment was put there for comparitive vision.
  14. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:


    It's an inovation that could unify the quest for parrallelism with the quest for single threaded performance. Whats wrong with that? If it's working already then all they need to do is add more core's and then devise a system to keep those cores fed. It would be like the string theory of the CPU world where everything is based off of a simple design which can be infinitly expanded. :wink:

    The quest for parallism has already come and gone, modern day compilers do a fantastic job of it already. As well current implementations of SPARC, MIPS, Cell, Itanium or anything RISC does a fantastic job at parallel execution. But that’s a single die execution environment, changing the page to dual core or higher adds significant code complexity roughly every core would add 125% more coding/debug time as well with the current limitations imposed by x86 machines; shifting, page access, memory allocation, branching, looping, pointer limitations, register renaming, instruction order limitations, vectorizeing limitations, stack size limitations, memory segmentation limits, array sizes, and the lack there of 32bit and 64bit registers. Hinder that progress of efficient code execution.

    As per single threaded performance we are starting to see the single thread performance slowing and normalizing, while dual and quad have promising thread performance, much of that that performance will be from the code base and compiler used. This currently looks to be already established in key development and media apps, but won’t likely ever make its way into the general computing environments as some would hope. Unless the software industry decided to have a performance war, which isn’t going to happen, because KISS rules all.

    But that’s not saying GCC or ICC compilers couldn’t create the binary for such adventitious endeavors. But even with the compilers and decent coding you will still need a very robust hardware configuration.

    Oh and the String theory doesn’t work since we are all running OOO machines.
    What?
  15. they seem to be copying everythin intel latly (good and bad), another?

    Quote:
    http://www.xtremesystems.org/forums/showthread.php?t=103636

    This isnt official but the general consensus is that it is true and there is some kind of virtualization built into AM2 chips that just needs a BIOS update so activate and it's coming after Conroe. Would be very interesting if this was true.
    Discuss
  16. Quote:
    You can tell its fake once they mention that MS will release a patch for it.

    Its not a fake as I found links to AMD's CEO speaking of using the FPU's as early as dual core K8L back in the very large conroe vs FX60 thread. MMM looked at my sites and found Revearse HyperThreading would later use the entire CPU. Its true that K8L wont be seeing the entire Revearse HyperThreading but FPU's extensions could make a big differance any case.

    What effects this will have in a multi threaded program is balancing the load to combat Intels HT load balancing. AMD will have a clear advantage at older games and single threaded programs.
  17. Quote:
    http://www.xtremesystems.org/forums/showthread.php?t=103636

    This isnt official but the general consensus is that it is true and there is some kind of virtualization built into AM2 chips that just needs a BIOS update so activate and it's coming after Conroe. Would be very interesting if this was true.
    Discuss



    Translated:

    Quote:
    AMD will let out "anti- -.Hyper-Threading" in this year: the secret weapon Socket AM2

    Even during April of this year appeared rumors about the fact that company AMD develops the technology, reverse on its action of the known technology Hyper-Threading from Intel. Let us recall that the latter makes possible for one processor to substitute by itself two virtual nuclei, and to divide between themselves the flows of data. Intel forewent further development of "virtual mnogoyadernosti" in favor of real mnogoyadernosti, but it does not exclude the possibility of the revival of this technology in the new performance.

    According to our personal information, obtained from the familiar with plans AMD of sources, already in this year the company will open access to technology, reverse on its action Hyper-Threading. If the latter divides the resources of one physical processor nucleus, then know-how AMD will make it possible to unite the resources of two physical nuclei for accelerating the tasks, which optimally work on the mononuclear processors. For example, this will make it possible to double a quantity of decoders, and the "united" processor will carry out six instructions for time. This already by itself can become not bad answer to the output of processors Conroe, and the debut of the corresponding technology for sure takes place on the eve on 24 July.

    The corresponding functionality is already build it the binuclear processors Athlon 64 x2 in execution Socket AM2. For its activation it will be required to only renew the driver of processor and BASIC INPUT-OUTPUT SYSTEM of maternal pay. Company Microsoft must let out appropriate patch for the operating systems, which will make it possible to receive two nuclei Athlon 64 X2 as one. By the way, according to the preliminary data, processor will be able to be switched into the "united" regime dynamically, depending on the type of the utilized application. It is no secret that many tasks as before win from the use of productive mononuclear processors, while not working at the lower frequencies binuclear processors.

    It is amusing, which itself AMD will be simultaneously occupied by the popularization of platform 4x4, calculated for the enthusiasts, thinkers of its existence without mnogozadachnosti. Judging by everything, two sufficient different approach will be spread on the different market niches. In any case, the possibility "to unite" two nuclei into one virtual will manage to the possessors of processors Athlon 64 x2 in execution Socket AM2 absolutely free of charge, if we do not consider possible expenditures for running off new BASIC INPUT-OUTPUT SYSTEM driver for the operating system.

    It is no secret that the start of technology Hyper-Threading sometimes caused reduction in the productivity, since two virtual nuclei began to dispute with the attempt to determine the priority of processing the flows of data. It is possible to assume that the antipode of technology Hyper-Threading from AMD will make it possible to avoid such annoying conflicts, and even will increase the operating speed of system.

    In proportion to the appearance of new information about this know-how AMD we will acquaint you with it on the pages of our site.




    If this is true, it will be a serious blow to Core 2. Imagine what 2 4200+ AM2s could do in SuperPi, much less 2 FX62s. 4x4 would be necesary i this case to keep 2 threads for the coming games for maximum scalability, but if the arbiter for the XBar is ready it would be a good 10-25% increase on single threaded apps.

    Looking at it fromthat perspective, the X2 could present itself as one contiguous core with block allocation for serialized tasks. Rather than depending on affinity it could depend on load per core. Since X2 uses HT to refresh the cache - recent post from JJ or such - coherency would be less of a problem and each core could work from L2. Of course the would need t be an efficient method for retiring data from each cache but marking the memory using something similar to "data-poisoning" where instead of not executing it causes a cache flush. It actually sounds like the way .Net handles memory but I digress.

    All in all, if it can actually combine execution between two cores with even 40% efficiency (above standard AM2 IPC), that would erase any advantage Core 2 has now in any single threaded apps. Imagine this in an Opteron F.

    I don't know if Intel wants to wait two years before updating.
  18. Imagine how much two FX-62s or two 4200s would cost.
    Also keep in mind that Core 2 is in its infancy. It can only get better. But you make valid points.
  19. Quote:
    Imagine how much two FX-62s or two 4200s would cost.
    Also keep in mind that Core 2 is in its infancy. It can only get better. But you make valid points.



    If you look at the article, it says this will happen at the same time the A64/X2 price cuts happen and it's a Rev F function, so I could have said 2 3800+s. If it gives 140% of current single thread perf at clock, it's awesome especially if it unlocks more DDR2 bandwidth.
  20. And also I remembered that dual core is recognized by the Task Mgr as 100% CPU where 50% is one core. Imagine then a quad core K8L with this ability. 8O
  21. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:


    It's an inovation that could unify the quest for parrallelism with the quest for single threaded performance. Whats wrong with that? If it's working already then all they need to do is add more core's and then devise a system to keep those cores fed. It would be like the string theory of the CPU world where everything is based off of a simple design which can be infinitly expanded. :wink:

    The quest for parallism has already come and gone, modern day compilers do a fantastic job of it already. As well current implementations of SPARC, MIPS, Cell, Itanium or anything RISC does a fantastic job at parallel execution. But that’s a single die execution environment, changing the page to dual core or higher adds significant code complexity roughly every core would add 125% more coding/debug time as well with the current limitations imposed by x86 machines; shifting, page access, memory allocation, branching, looping, pointer limitations, register renaming, instruction order limitations, vectorizeing limitations, stack size limitations, memory segmentation limits, array sizes, and the lack there of 32bit and 64bit registers. Hinder that progress of efficient code execution.

    As per single threaded performance we are starting to see the single thread performance slowing and normalizing, while dual and quad have promising thread performance, much of that that performance will be from the code base and compiler used. This currently looks to be already established in key development and media apps, but won’t likely ever make its way into the general computing environments as some would hope. Unless the software industry decided to have a performance war, which isn’t going to happen, because KISS rules all.

    But that’s not saying GCC or ICC compilers couldn’t create the binary for such adventitious endeavors. But even with the compilers and decent coding you will still need a very robust hardware configuration.

    Oh and the String theory doesn’t work since we are all running OOO machines.

    Well, I'm not supposed to understand it all; wonderful post, anyway.
    A second run of this "old" one http://forumz.tomshardware.com/hardware/modules.php?name=Forums&file=viewtopic&p=1087868#1087868, so it seems.

    Oh, and String Theory would work; it's also supposed to explain OoO on a lower level, that is.


    Cheers!
  22. If this turns out to be true...
    would a conroe still be the #1 choice of cpu compared with a variety of other amd chips?
  23. Quote:
    If this turns out to be true...
    would a conroe still be the #1 choice of cpu compared with a variety of other amd chips?

    Depends on the performance of AMD's solution I guess.
  24. You're a fool, both companies have made fantastic products.
  25. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:
    Maybe if you were'nt so bias. You know what Ycon nevermind there's no point in argueing with an intel fanboy of your calibur you've been brainwashed beyond belief even the mention of a company that is a rival to intel and the only thought's that come into your brain are Not...intel...bad...must...say...bad things! Geez dude stop trashing amd at every turn they had their turn in the spotlight and now intel's got their's. Do i trash conroe all the time? No! Cause i know it's gonna be good what if amd pull's out a rabbit from their ass like they did with k8? And let's say that this new architecture has a 10% performance increase over conroe? What would you do then huh? Would you still trash amd knowing that they are better or would you admit defeat and get along with the rest of us here?

    Splinter. Plank. Eye.

    Add some extra words and the concept should become clear. Was my post too long?
  26. Quote:
    You're a fool, both companies have made fantastic products.
    Finally someone agrees with me about him.
  27. "Reverse hyperthreading" is a joke, and that rumor is even more of a joke.

    Let's look at two possible approaches to "reverse hyperthreading", and how practical they are.

    The first "reverse hyperthreading" option is sharing the chips execution units. That is to say, a thread running in the first core can use the execution resources of the second. Sounds good and dandy, right? Not really. OOE (Out of Order Execution) already optimizes single threads as much as possible for parallelism, and they can barely make use of 3 execution units. There's a reason that chips have only been using 3 execution units for the past decade (and only recently begun to change with the Core uArch) - you can't really get a single thread to use more than that in 99% of the cases, regardless of how good your OOE processing is. Allowing the first core to use the execution resources of the second would be more or less useless, with the exception of a couple of very select synthetics designed to utilize the maximum number of execution engines by using a very simple stream of unrelated instructions. Even if the processor was somehow able to find an extra bit of parallelism, it isn't like chip-chip communications are one clock cycle. Even if AMD's crossbar does work (which has come into question with that recent article on X-bit), it certainly doesn't do communications in a single clock cycle. In other words, the instruction preprocessor would effectively have to find parallelism that isn't time sensitive. That is to say, the instruction can be delayed for 6 clock cycles and have it be sent to the other processor and back. Extremely unlikely.

    The second approach has to deal with branch prediction. As we all know, branch prediction isn't perfect. It's "very good", but not perfect. The idea is that you execute one branch possibility on core one, and another branch possibility on core two. This could possibly work - and have limited real world gains - but I personally think that the overhead involved would cancel out any gains. Modern processors are very good at branch prediction already. The average process has far less than 5% branch misprediction. So, with a short pipeline like the K8 has, you certainly wouldn't see very impressive results with this method. Not to mention, the overhead involved would be massive. The added complexity of switching processors for different branches (since it wouldn't make sense to run the process on core one, with the unexpected branch on core two, and then transfer the unexpected branch back to core one, because that would be the same as a pipeline flush anyway) back and forth would be problematic due to cache coherency issues.


    Either way, "reverse hyperthreading", practical or not, is not on current chips. There is simply no way. First of all, it would have leaked long before now. Second, why wouldn't they have enabled it already? That would be retarded to keep it a secret. Third, this is from a single source. A Russian site that is known to spread rumors. Not exactly a reliable source.
  28. "Reverse Hyperthreading" sure sounds like "Good Branch Prediction" to me, but I guess I'll wait and see until any credible evidence comes out for it.
  29. If its works why not just release it now instead of waiting?
  30. :lol: Seriously though, why even wait? They'd better off getting it out now and using that to play down core. BS rumour if you ask me.
  31. AMD is not greedy, and is not in the game to make profits, just the best processors under the sun! [/and pricing out of this world]
  32. I for one would really love for someone to point me to a link that says something more than a rumour, cause alot of AMD fans are clinging on to this for dear life.

    Is it too much to ask? too much time has been spent on something that hasnt been mentioned publicly from AMD or Intel, cause believe me, if AMD is reserching it, Intel is doing it also. and if it were credible intel would have leaked out that it was working on the same.

    So please, if anyone has anything link that has anything more than hearsay, please send it my way, i'd be more than gratfull.
  33. Quote:

    Is it too much to ask? too much time has been spent on something that hasnt been mentioned publicly from AMD or Intel, cause believe me, if AMD is reserching it, Intel is doing it also. and if it were credible intel would have leaked out that it was working on the same.

    So please, if anyone has anything link that has anything more than hearsay, please send it my way, i'd be more than gratfull.


    Intel has Mitosis:

    http://www.intel.com/technology/magazine/research/speculative-threading-1205.htm

    But it requires both hardware and software support. It's probably nothing more than a theoretical idea for everybody right now.
  34. Quote:
    AMD is not greedy, and is not in the game to make profits, just the best processors under the sun! [/and pricing out of this world]


    Are you drunk?
  35. I think, that such thing is not possible to happen somehow using the only technology of computing available today, procedural computing. Every instruction computed by any kind of a CPU today is done procedural by hardware logic, doing many tasks in order that can not be changed. For example, the procedure of any x86 CISC CPU is done by minimum of fetching, decoding, dispatching, scheduling, executing and retireing. There is no way to change this order or perform these tasks in parallel. At this level "reverse hyperthreading" should do its job. The HyperThreading is the oposite at the same level, it just fetches, decodes, dispatches, schedules, executes and retires instructions from 2 threads on one die.

    OOO execution, Speculative threading and branching are not "reverse hyperthreading". Those techniques are not decreasing the time needed to execute 1 instruction. They can help the CPU to be more efficient, reducing the "bubbles" in the pipeline, but they are useless whenever the pipeline is full.

    If one thread can be splited by many threads and proceesed in parallel that is multithreading, not "reverse hyperthreading". Today programmers are learning to write software that can be easy processed on multiple cores as much as possible sharing the tasks equal. In future all apps will be multithreaded, there will be no need for singlethread CPU performance. Why should anyone try to invent impossible technology that will not be used?

    If AMD are after such thing, I am 10000000% sure that they will exploatate such marketing years before it will be released. They never mentioned such thing for K8L or K8(4x4, 65536x65536 or whatever they will name the old K8). They just made a huge noise, rumors, speculations, stories and other marketing about the useless 4x4 that appears to me like the most stupid thing that AMD did in their own history. It is just a try to promote them selves as leader and they are not. They actually never were.
  36. Mitosis is actually not anything like "reverse hyperthreading" (the name that AMD fanatics use to name their little smoke-hang out party).

    According to that article, for the most part, Intel was trying to address the problem with today compiler being too conservative on turning single thread applications into multi-thread for multi cores platform. And the perfomance gain in running compiled single thread on multi-cores is not as high as expected. Therefore, they are working on Mitosis as a solution to make these compilers being less conservative on dividing the workloads of a single thread into a highly parallel application. A new design is needed on the hardware side to save the rare situation where 2 codes are trying to access the same memory area ( as an example).

    Mitosis sounds like an enhance version of multi thread application on both hardware and software. Reverse hyperthreading sounds much like BS to me now.
  37. Thanks!
  38. Quote:
    They are just trying to pull software engineers back into programming single-threaded software but it wont work.

    Maybe AMD supports an anti-technological-progress view? :lol:


    It's an inovation that could unify the quest for parrallelism with the quest for single threaded performance. Whats wrong with that? If it's working already then all they need to do is add more core's and then devise a system to keep those cores fed. It would be like the string theory of the CPU world where everything is based off of a simple design which can be infinitly expanded. :wink:

    The quest for parallism has already come and gone, modern day compilers do a fantastic job of it already. As well current implementations of SPARC, MIPS, Cell, Itanium or anything RISC does a fantastic job at parallel execution. But that’s a single die execution environment, changing the page to dual core or higher adds significant code complexity roughly every core would add 125% more coding/debug time as well with the current limitations imposed by x86 machines; shifting, page access, memory allocation, branching, looping, pointer limitations, register renaming, instruction order limitations, vectorizeing limitations, stack size limitations, memory segmentation limits, array sizes, and the lack there of 32bit and 64bit registers. Hinder that progress of efficient code execution.

    As per single threaded performance we are starting to see the single thread performance slowing and normalizing, while dual and quad have promising thread performance, much of that that performance will be from the code base and compiler used. This currently looks to be already established in key development and media apps, but won’t likely ever make its way into the general computing environments as some would hope. Unless the software industry decided to have a performance war, which isn’t going to happen, because KISS rules all.

    But that’s not saying GCC or ICC compilers couldn’t create the binary for such adventitious endeavors. But even with the compilers and decent coding you will still need a very robust hardware configuration.

    Oh and the String theory doesn’t work since we are all running OOO machines.
    What?

    Moo.
  39. Quote:
    If its works why not just release it now instead of waiting?


    Well if you follow BaronMatrix logic on why AMD does not release 65 nm today it is because they don't need to... they can simply wait and time it at the most strategic point in the market cycle. Sorta an "anti-revenue loss" measure if you will, that's it when revenue starts plummeting they will implement anti-revenue_loss threading :) ...


    I have never said that. I said "the word was" they could release it sooner but they would have a similar problem to intels where they are competing too much with their current stock.

    it takes almost a year to change over. If they really have this Virtual core tech, they really won't need to go 65nm to keep up with Intel.
  40. Quote:
    If its works why not just release it now instead of waiting?


    Well if you follow BaronMatrix logic on why AMD does not release 65 nm today it is because they don't need to... they can simply wait and time it at the most strategic point in the market cycle. Sorta an "anti-revenue loss" measure if you will, that's it when revenue starts plummeting they will implement anti-revenue_loss threading :) ...


    I have never said that. I said "the word was" they could release it sooner but they would have a similar problem to intels where they are competing too much with their current stock.

    it takes almost a year to change over. If they really have this Virtual core tech, they really won't need to go 65nm to keep up with Intel.
  41. Quote:
    I for one would really love for someone to point me to a link that says something more than a rumour, cause alot of AMD fans are clinging on to this for dear life.

    Is it too much to ask? too much time has been spent on something that hasnt been mentioned publicly from AMD or Intel, cause believe me, if AMD is reserching it, Intel is doing it also. and if it were credible intel would have leaked out that it was working on the same.

    So please, if anyone has anything link that has anything more than hearsay, please send it my way, i'd be more than gratfull.

    Here's one of the links I found but its 8 months old so some of the future goals have moved to comming soon.
    http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2565
    I wish I could find more of my old links where the CEO said the FPU extensions will arrive in the K8L design and the entire cores will be used by late quad early octual cores.
  42. I don't think it is an anti-paralleling scheme at all. From what I can tell from the writeup, if true, they would be trying to use a quad core CPU as two dual-core CPU's that can do 6 IPC each, running a set of instructions across two cores (or more) in the same clock cycle. Or something similar to that. I think that is the goal of their quad core CPU since very very vew people in the mainstream will see the benefit of two more cores. I would guess that they would have to run the clocks slightly out of phase to allow the communication between the chips to happen. If they can pull it off, I'll be impressed.
  43. I think it's a really good idea, and at some point it may be possible. It might be true. But, as it has been pointed out, the site the rumor (I emphasize the word rumor) comes from is a known BSpreader. If AMD can pull this off, there goes all the hard work Intel has done by unofficially releasing Core 2/Conroe benchmarks.

    Although, this move may undermine all attempts to create multithreaded applications - if emphasis is placed back on single threads, where will we be again? Multicore will only be useful for things other than gaming - a big selling point for AMD. They could be shooting themselves in the leg in the long run.

    At least until quad-cores are out, in which case the race for multiple threads/SMP-aware apps will be back on.

    I would definitely get the patch should it be real - good idea for performance now, even if it may slow progression later.
  44. Quote:
    This could possibly work - and have limited real world gains - but I personally think that the overhead involved would cancel out any gains.

    I agree.

    It seems that the point of the article is saying that with this idea, 2 AMD processors can make a 6-way architecture virtual CPU.
    Since Conroe has a 4-way, hence this reverse-hyperthreading must be better, etc.

    But that's never exactly the case as we all know. It looks like they're trying to use this to compete w/ all the processor makers, not just intel... Perhaps trying to take on RISC cpus or something?

    If this is real, it'll probably make some difference in some benchmarks. I doubt it would give a benefit across the board.

    It'll be interesting to see how the OS will handle it. Will it see just 1 CPU? Or 2 CPUs and the reverse stuff is done at an application level?
  45. Quote:
    :lol: Seriously though, why even wait? They'd better off getting it out now and using that to play down core. BS rumour if you ask me.


    Yeah, but how serious can we really treat the subject. K8MAN is fair, reasonable and honest for the most part, good discussion buddy so it would be nice to give him a good forum to bring up ideas, unfortunately this is being overshadowed by Baron who has no reasonable sense on these matters -- according to Baron AMD is ready to pounce -- though they are cutting prices, production lines, and whizzing out last minute gimmicks in a manner defining panick in every sense of the word --- everything seems hunky-dory especially when we won't need to worry about Core 2 until what November the way he keeps floating the date :) ....


    Why dont't yout ry keeping my name OUT OF YOUR MOUTH? It seems to me that you are just upset because I turn out to be right so much. Get used to it.

    I haven't floated anything you punk.

    Keep my name out of your mouth unless commenting to me. D@@*head.
  46. Quote:
    :lol: Seriously though, why even wait? They'd better off getting it out now and using that to play down core. BS rumour if you ask me.


    Yeah, but how serious can we really treat the subject. K8MAN is fair, reasonable and honest for the most part, good discussion buddy so it would be nice to give him a good forum to bring up ideas, unfortunately this is being overshadowed by Baron who has no reasonable sense on these matters -- according to Baron AMD is ready to pounce -- though they are cutting prices, production lines, and whizzing out last minute gimmicks in a manner defining panick in every sense of the word --- everything seems hunky-dory especially when we won't need to worry about Core 2 until what November the way he keeps floating the date :) ....


    Why dont't yout ry keeping my name OUT OF YOUR MOUTH? It seems to me that you are just upset because I turn out to be right so much. Get used to it.

    I haven't floated anything you punk.

    Keep my name out of your mouth unless commenting to me. D@@*head.

    Moo.
  47. This is from RealWorldTech Forums; and is posted by David Kanter:-

    Quote:
    Not Possible.

    So, just think about how a MPU works. Look at the diagrams I have for my Core microarchitecture article:

    http://www.realworldtech.com/page.cfm?ArticleID=RWT030906143144&p=3

    Each processor separately fetches, issues, reorders, executes and then retires instructions. Now ask yourself what happens if we split up the instruction stream?

    Suppose instruction A on core 1 needs data that instruction B on core 2 is using. Then you have to send the data between the two, which will take at least 3-5 cycles.

    So, that doesn't really work. Moreover, suppose one core mispredicted a branch and has to flush the pipe, how would it let the other one know?

    It can't really. So there is no way that two separate cores can operate on the same instruction stream and both retire instructions.

    What you might able to do is have each processor operate on the same instruction stream but only let one of them actually write to the architectural state.

    So one core basically acts as a branch calculator and instruction/data prefetcher. However, that doesn't work if the two cores don't share caches and cannot communicate.

    The bottom line is that if you really look at what they are suggesting, it's pretty unreasonable. Moreover, if they were to do that, AMD would have to basically change everything about the K8.

    There are lots of ideas out there that involve one instruction stream working across many 'mini cores'. If you are interested, use citeseer or google to look up "Multiscalar processors" and "trace processors". I'd also recommend investigating skip-ahead and dynamic multithreading.

    DK
  48. Quote:
    :lol: Seriously though, why even wait? They'd better off getting it out now and using that to play down core. BS rumour if you ask me.


    Yeah, but how serious can we really treat the subject. K8MAN is fair, reasonable and honest for the most part, good discussion buddy so it would be nice to give him a good forum to bring up ideas, unfortunately this is being overshadowed by Baron who has no reasonable sense on these matters -- according to Baron AMD is ready to pounce -- though they are cutting prices, production lines, and whizzing out last minute gimmicks in a manner defining panick in every sense of the word --- everything seems hunky-dory especially when we won't need to worry about Core 2 until what November the way he keeps floating the date :) ....


    Why dont't yout ry keeping my name OUT OF YOUR MOUTH? It seems to me that you are just upset because I turn out to be right so much. Get used to it.

    I haven't floated anything you punk.

    Keep my name out of your mouth unless commenting to me. D@@*head.

    Jack doesn't need me to defend him, since he is quite capable himself to... but you asked for it, by posting your thoughts that Conroe will be delayed based on sketchy info of questionable reputation, which is contrary to most reputable reports...
    Heck, if you get fired up this easily, you might need to change your user name to Red Baron... since thin skin will make you a target that a barrage of attacks will inevitably come your way... and shoot you down! :P :lol:
  49. Quote:
    It seems to me that you are just upset because I turn out to be right so much.


    LOL!!!!!!!!!!!!!!!!!!!!!!!!!!!
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