AMD "reverse hyperthreading" speculation...

cxl

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Just a thought:

Nobody knows what AMD's "reverse" should really mean, so let us speculate...

The poptular explanation that CPU somewhat "joins" two cores and increases IPC per single is very unlikely (anybody knowing a little about CPU architecture knows that).

Now facts: AMD speaks about "reusing parts of CPU for single threaded apps". AMD trashed 2x1MB cache CPUs and introduces 2x256KB cache CPUs.

Speculation:

"reverse hyperthreading" will in fact dynamically (using software driver) switch one's core L2 cache to another core - means if there is single threaded app running, this feature will provide it twice as much cache (1MB or 512KB for new 3600) (maybe twice as much datapath too).
 

joset

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Just a thought:

Nobody knows what AMD's "reverse" should really mean, so let us speculate...

Humm... you're late. There are about half a dozen threads on it.

And, it's known as "Speculative Threading" or "Speculative Precomputation".


Cheers!
 

gudodayn

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Its also known as Speculative FUD.

LOL damn, that FUD is everywhere, everywhere, i see FUD people from INtel and AMD

Absolutely..........Intel FUD / AMD FUD, its everywhere .......... activities from both camps are high!!!!

Unless you're the CPU Chief Engineer for Intel or AMD........dont comment on what it can and cant do!!!!

Dont act like you know!!!

Dont speculate, give us benchmarks.....oh~~~it aint out yet so you cant be sure either??
 

Mike995

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Reverse hyper threading is going to be soundly countered by Intel core multiplexing, Intel has this fight covered from all directions, and I dont think amd is suprising them one bit. And from the looks of it multiplexing is completly available and supported by intel on the conroe launch, it is possible with the new bios for the 975x bad axe, and all conroes support it. Amd if anything is too late with their lame ass reverse hyperthreading. http://www.matbe.com/actualites/13666/reverse-ht-core-multiplexing/
 

BaronMatrix

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Just a thought:

Nobody knows what AMD's "reverse" should really mean, so let us speculate...

The poptular explanation that CPU somewhat "joins" two cores and increases IPC per single is very unlikely (anybody knowing a little about CPU architecture knows that).

Now facts: AMD speaks about "reusing parts of CPU for single threaded apps". AMD trashed 2x1MB cache CPUs and introduces 2x256KB cache CPUs.

Speculation:

"reverse hyperthreading" will in fact dynamically (using software driver) switch one's core L2 cache to another core - means if there is single threaded app running, this feature will provide it twice as much cache (1MB or 512KB for new 3600) (maybe twice as much datapath too).

Since AMD nor Intel will coin it I'd rather call it DMT (Dynamic MultiThreading).

After reading the latest "unversity research" it will be a boon to any company who uses it.

Assigning for loops would improve game matrix programming in a multithreaded scenario at least 40-50% - especially using optimized time slicing through the partition interface.


Optimization and coordinated scheduling of prefetch (L1-L2, L2-RAM) and the aleady existent (?) parallel decoder/instruction units would allow for multiple instructuion flows in a superscalar fashion.


I would still like to hear if implementation has been considered much less accomplished.
 

BaronMatrix

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whats FUD? :oops: :)
it is what BaronMatrix is saying.

link?

I actually printed the flow diagrams from the patent and read several of the othe rlinks provided in one or nother of those threads. Google "optimize ime slicing", thead control unit, buffer tags, speculative loop, or just take about however long and review each of these threads for the links to the proof.


Oh yeah that's right the Smart Power 2.0 costs $69 and the True Power 2.0 costs $89.

:oops:
 

gOJDO

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whats FUD? :oops: :)
it is what BaronMatrix is saying.

link?

I actually printed the flow diagrams from the patent and read several of the othe rlinks provided in one or nother of those threads. Google "optimize ime slicing", thead control unit, buffer tags, speculative loop, or just take about however long and review each of these threads for the links to the proof.


Oh yeah that's right the Smart Power 2.0 costs $69 and the True Power 2.0 costs $89.

:oops:
Very good, but you remained to be the most ignorant and the most stupid member on this forum.
 

BaronMatrix

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whats FUD? :oops: :)
it is what BaronMatrix is saying.

link?

I actually printed the flow diagrams from the patent and read several of the othe rlinks provided in one or nother of those threads. Google "optimize ime slicing", thead control unit, buffer tags, speculative loop, or just take about however long and review each of these threads for the links to the proof.


Oh yeah that's right the Smart Power 2.0 costs $69 and the True Power 2.0 costs $89.

:oops:
Very good, but you remained to be the most ignorant and the most stupid member on this forum.


remained to be is improper grammar. You may have been looking for "still remain the"


Oh yeah someone said Intel IGP doesn't suck so your grammar can be atrocious.
 

gOJDO

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remained to be is improper grammar. You may have been looking for "still remain the"


Oh yeah someone said Intel IGP doesn't suck so your grammar can be atrocious.
It is a fact, my english grammar sux. But that does not change the fact that you are ignorant stupid lair with very low IQ and no knowledge.
 

kukito

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It is a fact, my english grammar sux. But that does not change the fact that you are ignorant stupid lair with very low IQ and no knowledge.

Aren't you from Macedonia? English isn't your native tongue, is it? How many languages do you speak? Considering that, I would say your English grammar is quite good. I wonder how BM's grammar would be in Macedonian, Serbo-Croatian or Albanian.