Just a thought:
Nobody knows what AMD's "reverse" should really mean, so let us speculate...
The poptular explanation that CPU somewhat "joins" two cores and increases IPC per single is very unlikely (anybody knowing a little about CPU architecture knows that).
Now facts: AMD speaks about "reusing parts of CPU for single threaded apps". AMD trashed 2x1MB cache CPUs and introduces 2x256KB cache CPUs.
Speculation:
"reverse hyperthreading" will in fact dynamically (using software driver) switch one's core L2 cache to another core - means if there is single threaded app running, this feature will provide it twice as much cache (1MB or 512KB for new 3600) (maybe twice as much datapath too).
Nobody knows what AMD's "reverse" should really mean, so let us speculate...
The poptular explanation that CPU somewhat "joins" two cores and increases IPC per single is very unlikely (anybody knowing a little about CPU architecture knows that).
Now facts: AMD speaks about "reusing parts of CPU for single threaded apps". AMD trashed 2x1MB cache CPUs and introduces 2x256KB cache CPUs.
Speculation:
"reverse hyperthreading" will in fact dynamically (using software driver) switch one's core L2 cache to another core - means if there is single threaded app running, this feature will provide it twice as much cache (1MB or 512KB for new 3600) (maybe twice as much datapath too).