Sign in with
Sign up | Sign in
Your question

amd brisbane - K8L?

Last response: in CPUs
Share
July 3, 2006 5:32:55 AM

someone correct me if im wrong
amd brisbane is a K8 Revision G core & not a K8L core & features either 2x1MB L2 cache or 2x512KB L2 cache and has a launch date 12/06
dailtytech
prices listed here
can anybody confirm a K8L dual core and release dates....

been waiting for a year. ive had it!

More about : amd brisbane k8l

July 3, 2006 5:36:39 AM

Thats not the launch date, I think its shipping or something. Launch is early next year.
July 3, 2006 5:51:51 AM

well, wot about the K8L dual cores?
got any news?
Related resources
July 3, 2006 5:54:35 AM

Could you be more specific?

Ah found the slide. Link.
July 3, 2006 6:18:50 AM

There haven't been any specific dates as to when K8L is shipping, however, AMD's CEO Hector Ruiz has said, "We're going to introduce a really new architecture that will work well with our partners for the best performance. We're going to start sampling it at the end of 2007 and roll it out in 2008," in an interview with BusinessWeek. From this, we can infer that by next generation, he's referring to K8L, as there is basically no information out there about AMD's future plans outside of K8L. It's a little vague, as he could also be reffering to their Torrenza and not to the actual architecture of their chips (read the article and you'll see what I'm talking about; it's quite interesting too, reading an interview where the CEO of AMD basically bashes and talks smack about Intel!)
July 3, 2006 4:26:46 PM

AMD has stopped offering 2x1 MB L2 cache offerings and I doubt they will re-introduce those models anytime soon.
July 3, 2006 8:27:36 PM

Quote:
someone correct me if im wrong
amd brisbane is a K8 Revision G core & not a K8L core & features either 2x1MB L2 cache or 2x512KB L2 cache and has a launch date 12/06
dailtytech
prices listed here
can anybody confirm a K8L dual core and release dates....

been waiting for a year. ive had it!


Rev G is due in Dec. K8L is due around June of next year.
July 3, 2006 8:27:58 PM

Quote:
someone correct me if im wrong
amd brisbane is a K8 Revision G core & not a K8L core & features either 2x1MB L2 cache or 2x512KB L2 cache and has a launch date 12/06
dailtytech
prices listed here
can anybody confirm a K8L dual core and release dates....

been waiting for a year. ive had it!


Rev G is due in Dec. K8L is due around June of next year.
July 3, 2006 9:30:03 PM

Can you link to any info thats states K8L is out next year and not 2008?
July 3, 2006 9:48:48 PM

Quote:
Can you link to any info thats states K8L is out next year and not 2008?

no he can't.
July 3, 2006 10:18:05 PM

From that you can assume K8L? What are you talking about 08? Come on..... read much?
July 4, 2006 5:47:06 AM

Everything that AMD has said seems to point to K8L in 2008. They may try to move it up to 07, but they are probably blowing smoke.

Rev G Athlons are to have some solid core revisions that may help them match their IPC to that of Core. They just wont scale high enough though. Higher end quad cores may be a different story as Intel doesnt have much left in their FSB. To make things worse Kentsfield is an MCM which puts 2 loads on the FSB, meaning they are probably stuck at 1066mhz.

Does anyone know if K8L revisions will be applied to DC chips? AMD has said they are 'native quad core'.
July 4, 2006 6:03:36 AM

Quote:
Everything that AMD has said seems to point to K8L in 2008. They may try to move it up to 07, but they are probably blowing smoke.

Rev G Athlons are to have some solid core revisions that may help them match their IPC to that of Core. They just wont scale high enough though. Higher end quad cores may be a different story as Intel doesnt have much left in their FSB. To make things worse Kentsfield is an MCM which puts 2 loads on the FSB, meaning they are probably stuck at 1066mhz.

Does anyone know if K8L revisions will be applied to DC chips? AMD has said they are 'native quad core'.



I'm looking for the inteviews that say K8L is for H207 and a totally new "not-K8" architecture is due sometime in 2008. IF K8L lives up to the specs, it will eclipse Core 2, with 1.5x FP, single cycle SSE128, 4 decoders, enhanced execution units @ 65nm,

That sounds as good as Core 2s specs and is in ADDITION to what K8 already does.

According to the latest intrerviews it WILL BE applied to dual core (for market positioning - Opteron and MAYBE FX will be quad, high end X2 will be dual K8L and everything else will be AM2. I'm hoping that single core does go away, though.

I mean a lineup (AMD or Intel) of ULV dual core mobile, LV dual core HTPC, Gaming dual core, extreme gaming dual core, entry level dual core svr/wksta, mid range dual/quad svr, high end quad svr.

I figure both companies will be well on the way by Apr 07. Because of certain advantages, I give AMD 7-3 for giving Intel fits until the next arch.
July 4, 2006 6:22:02 AM

Quote:
I'm looking for the inteviews that say K8L is for H207 and a totally new "not-K8" architecture is due sometime in 2008.


I have trouble believing that AMD would invest in K8L and then replace it again in less than a year. Thats assuming that K8L will be taped out soon. If tape out take longer than Jacks projections, it would push it even further back. Running K8L, which may only be available at the high end, and then switching gears to K10 that quickly cannot be economial.

If K8L is to replace Athlon/AX2/AX4? eventually and K10 would comprise of the FX/Opteron lines than that could be feasable. That would fit in line with AMDs stance of non-uniform microarchectures across product lines. The only problem would be a return of Opteron socket FX series.
July 4, 2006 10:09:13 AM

Quote:
with 1.5x FP


No.

Quote:
4 decoders


No.
July 4, 2006 11:43:56 AM

Quote:
with 1.5x FP


No.

Hmm...
K8L will be able to execute 4 FPU DP (64bit) operations per cycle (not counting load/store), that's 2x the performance of K8.
I don't remember Core having such a performance increase (i'm talking about FPU ops, not SSE FP ops), but i might be mistaken.


Quote:

4 decoders


No.
"Hmm..." again.
In fact, all it has been declared, is that K8L will be able to FETCH 32byte per clock instead of 16.
Now, this could either mean that K8L will be able to fetch and decode *very* long x86 instructions (though this is unlikely, as most of these instructions are legacy/unused in modern code) or that it will be able to decode more than 3 instructions per clock.
Though, this is still only speculation though.

However, i'm skeptical toward these "K10 in 2008" rumors.
Sure this was scheduled to happen, but i've seen only very old articles (1 year old or more) saying so.
In the latest AMD roadmap, according to the Anandtech article quoted by BaronMatrix, AMD speaks about "core update" in 2008.
That doesn't sound like a completely new core architecture, as K10 was supposed to be.
Also AMD has recently spoken about an "evolutionary, not revolutionary" approach..
July 4, 2006 11:49:22 AM

Quote:
Hmm...
K8L will be able to execute 4 FPU DP (64bit) operations per cycle (not counting load/store), that's 2x the performance of K8.
I don't remember Core having such a performance increase (i'm talking about FPU ops, not SSE FP ops), but i might be mistaken.


Hes said 1.5 FP of core 2. Core can do 4 DP FP per cycle just like K8L. Thats not 1.5x last time I checked.

Quote:
"Hmm..." again.
In fact, all it has been declared, is that K8L will be able to FETCH 32byte per clock instead of 16.
Now, this could either mean that K8L will be able to fetch and decode *very* long x86 instructions (though this is unlikely, as most of these instructions are legacy/unused in modern code) or that it will be able to decode more than 3 instructions per clock.
Though, this is still only speculation though.


Not a very good arguement there. If it did they'd have mentioned it when they were handing out K8L details.
July 4, 2006 11:55:04 AM

I keep reading on sites that K8L is expected in Q1 of next year.... but who really knows since AMD isn't releasing any hard dates, it's all speculation and possible insider info until it comes from the horses mouth.
July 4, 2006 11:58:08 AM

I really doubt it'll be Q1, I'm expecting june at the earliest. Revison G isn't on sale till Q1 2007.
July 4, 2006 12:08:19 PM

Quote:
Hmm...
K8L will be able to execute 4 FPU DP (64bit) operations per cycle (not counting load/store), that's 2x the performance of K8.
I don't remember Core having such a performance increase (i'm talking about FPU ops, not SSE FP ops), but i might be mistaken.


Hes said 1.5 FP of core 2. Core can do 4 DP FP per cycle just like K8L. Thats not 1.5x last time I checked.

Nope.
Core (unlike K8L) can do only 2 DP FP per cycle (one FADD and one FMUL).
(Ars Technica)
Core can do 4DP FP per cycle, as K8L, only if using SSE code.
So this depends on the application, even though many (most?) applications use SSE for this purpose nowadays.
But i think the confusion on the effective speedup is generated from this.

Quote:
"Hmm..." again.
In fact, all it has been declared, is that K8L will be able to FETCH 32byte per clock instead of 16.
Now, this could either mean that K8L will be able to fetch and decode *very* long x86 instructions (though this is unlikely, as most of these instructions are legacy/unused in modern code) or that it will be able to decode more than 3 instructions per clock.
Though, this is still only speculation though.


Not a very good arguement there. If it did they'd have mentioned it when they were handing out K8L details.
Well, they did double the fetch bandwidth (official statement), and i'm sure they did this for a purpose.
CPU are designed based on workload statistics gathered from real world usage patterns, and increasing fetch capacity makes sense only if you also increase decode capacity (unless the existing decoders were starved).
July 4, 2006 12:17:41 PM

Quote:
Nope.
Core (unlike K8L) can do only 2 DP FP per cycle (one FADD and one FMUL).
(Ars Technica)
Core can do 4DP FP per cycle, as K8L, only if using SSE code.
So this depends on the application, even though many (most?) applications use SSE for this purpose nowadays.
But i think the confusion on the effective speedup is generated from this.


Meh, x87 is practically dead, its been replaced with SSE in x86-64. :wink:

Quote:
Well, they did double the fetch bandwidth (official statement), and i'm sure they did this for a purpose.
CPU are designed based on workload statistics gathered from real world usage patterns, and increasing fetch capacity makes sense only if you also increase decode capacity (unless the existing decoders were starved).


Read the last thing your wrote.
July 4, 2006 12:39:45 PM

Quote:

Meh, x87 is practically dead, its been replaced with SSE in x86-64. :wink:

Agreed.
But my point was just to explain where the 1.5x statement might come from, not to hype K8L.
Yet, if AMD felt the need to boost x87 floating point, probably there will be a few application which can benefit from it.

Quote:
Well, they did double the fetch bandwidth (official statement), and i'm sure they did this for a purpose.
CPU are designed based on workload statistics gathered from real world usage patterns, and increasing fetch capacity makes sense only if you also increase decode capacity (unless the existing decoders were starved).


Read the last thing your wrote.
Hmmm.. yup could be, but Intel decided to fit Conroe with 3 simple decoders and 1 complex one.
Intel didnt decide to fit 3 complex decoders as AMD did, so i believe today's code is not composed of very long instructions.
When AMD fitted the K7 (then K8 ) with 3 complex decoders, it was more than 5 years ago, when legacy code still had its importance.
But then again, this is all speculation.
We'll see when more details on K8L will be released, but a shift from 16byte to 32byte fetching is no small change, IMO.
July 4, 2006 1:43:52 PM

Quote:
I'm looking for the inteviews that say K8L is for H207 and a totally new "not-K8" architecture is due sometime in 2008.


I have trouble believing that AMD would invest in K8L and then replace it again in less than a year. Thats assuming that K8L will be taped out soon. If tape out take longer than Jacks projections, it would push it even further back. Running K8L, which may only be available at the high end, and then switching gears to K10 that quickly cannot be economial.

If K8L is to replace Athlon/AX2/AX4? eventually and K10 would comprise of the FX/Opteron lines than that could be feasable. That would fit in line with AMDs stance of non-uniform microarchectures across product lines. The only problem would be a return of Opteron socket FX series.


This is what their roadmap says. The next chip at 45nm maybe 6-8 cores so 4 cores will move down and 2 cores etc.

They have uniformity around chip families. The sockets are just slightly different.

Die shrinks have the advantage of making it possible to produce the chips for less. 65nm allows for twice the amount of chips per wafer.


Turion is splitting off though because they now have a mobile design team that works separate from server/desktop team.
July 4, 2006 1:49:21 PM

Quote:
Hmm...
K8L will be able to execute 4 FPU DP (64bit) operations per cycle (not counting load/store), that's 2x the performance of K8.
I don't remember Core having such a performance increase (i'm talking about FPU ops, not SSE FP ops), but i might be mistaken.


Hes said 1.5 FP of core 2. Core can do 4 DP FP per cycle just like K8L. Thats not 1.5x last time I checked.

Quote:
"Hmm..." again.
In fact, all it has been declared, is that K8L will be able to FETCH 32byte per clock instead of 16.
Now, this could either mean that K8L will be able to fetch and decode *very* long x86 instructions (though this is unlikely, as most of these instructions are legacy/unused in modern code) or that it will be able to decode more than 3 instructions per clock.
Though, this is still only speculation though.


Not a very good arguement there. If it did they'd have mentioned it when they were handing out K8L details.



But K8L hs two FP units and double SSE FP @ 128. 4 complex decoders will increase their IPC by 25% or more.

Just admit it K8L will rock. It doesn't mean Intel sucks.
July 4, 2006 1:54:07 PM

BTW


from AnandTech:

On a very slightly lower level architecture side, we have a slide showing the overview of AMD's next server class processor with 4 cores based on K8L. Features include a shared L3 cache, "enhanced IPC" cores, OoO (Out of Order) loads, wider data paths, HT-3 (the third version of HyperTransport), and support for DDR2 (and DDR3 or FBDIMMS in the future). Details on some of these enhancements were way too light, especially on the IPC (Instructions Per Clock) front.





Cache enhancements include the capability to support 2x128-bit loads per cycle from the 64k L1 cache (which is half the size of the K8 L1 cache), and a shared L3 cache which will scale up from its introduction at 2MB. The shared L3 cache will help with features like node interleaving on multiprocessor systems as well as multithreaded apps which make use of shared data. We are still waiting for more detailed data on the cache architecture. It isn't clear whether the caches are all exclusive, and we would like to know more about associativity as well.

At a lower level, we have a block diagram of the compute core for K8L CPUs. Again, this diagram is a bit oversimplified, but we can see a few key features of the architecture. On the FP side, the CPU is able to handle 2x128-bit floating point or SSE operations per clock. While this isn't quite as flexible as Intel's Core with its 3 SSE units, AMD's K8L will be able to handle 4 double precision floating point operations per clock. . (Current K8 chips can only do 1x128/2x64-bit SSE instructions per clock.)




IF you go to the die shot slide on this page you will see the 32B prefetch.

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=276...
July 4, 2006 1:54:19 PM

Quote:

This is what their roadmap says.

Could you please provide a link to a recent article showing the word "K10" in AMD's roadmap for 2008?
July 4, 2006 1:56:28 PM

Quote:
Could you please provide a link to a recent article showing the word "K10" in AMD's roadmap for 2008?

No, he can't.
July 4, 2006 1:58:46 PM

Quote:

But K8L hs two FP units and double SSE FP @ 128. 4 complex decoders will increase their IPC by 25% or more.

Just admit it K8L will rock. It doesn't mean Intel sucks.

Nope, nowhere has been stated that K8L will have 4 complex decoders.
The only fact for now, is that it will be able to fetch 32byte instead of 16; how this fetched data will be decoded, is still unknown.
And even if it did, this does not necessarily translate into an IPC increase of 25% or more.
At the moment, we can only speculate that K8L will be in the same performance ballpark as Conroe (for single threaded performance), but nothing else.
July 4, 2006 2:27:21 PM

Quote:

This is what their roadmap says.

Could you please provide a link to a recent article showing the word "K10" in AMD's roadmap for 2008?


They have yet to name it. It could be K10, it could be some other code name. As of now they just call it the next generation core.
July 4, 2006 2:31:14 PM

Actually, the latest rumor i could find, is from the Inquirer, and says that K10 project is probably cancelled. (Link)
Then there are ancient news from 2003, which talk about a K10 which we surely never see (10GHz, huge caches, 8 issue). (Link)
And some other rumors about K10 featuring this so called "reverse hyperthreading".
(Link)
Pretty much all uninteresting stuff.
July 4, 2006 2:32:05 PM

Quote:

But K8L hs two FP units and double SSE FP @ 128. 4 complex decoders will increase their IPC by 25% or more.

Just admit it K8L will rock. It doesn't mean Intel sucks.

Nope, nowhere has been stated that K8L will have 4 complex decoders.
The only fact for now, is that it will be able to fetch 32byte instead of 16; how this fetched data will be decoded, is still unknown.
And even if it did, this does not necessarily translate into an IPC increase of 25% or more.
At the moment, we can only speculate that K8L will be in the same performance ballpark as Conroe (for single threaded performance), but nothing else.


I'm looking for the link. You make it sound like a physics problem would prevent them from ADDING ONE MORE DECODER.
July 4, 2006 2:34:29 PM

Quote:
with 1.5x FP


No.

Quote:
4 decoders


No.


1.5X K8 stupid. Yes the word was they would add a decoder. I guess we'll see.
July 4, 2006 2:35:48 PM

Quote:

They have yet to name it. It could be K10, it could be some other code name. As of now they just call it the next generation core.

Wait a min.
Your quote from Anandtech (which i consider a reputable source) speaks about a "Next Generation Core" for 2007, which is obviously K8L (and the whole article is about it).
For 2008, only a "Core Update" is mentioned, which does not sound like a complete core redesign to me.
July 4, 2006 2:36:12 PM

Quote:
Actually, the latest rumor i could find, is from the Inquirer, and says that K10 project is probably cancelled. (Link)
Then there are ancient news from 2003, which talk about a K10 which we surely never see (10GHz, huge caches, 8 issue). (Link)
And some other rumors about K10 featuring this so called "reverse hyperthreading".
(Link)
Pretty much all uninteresting stuff.



What does it matter what the codename is? DMT is more exciting than anything else out right now.
July 4, 2006 2:38:54 PM

Quote:

They have yet to name it. It could be K10, it could be some other code name. As of now they just call it the next generation core.

Wait a min.
Your quote from Anandtech (which i consider a reputable source) speaks about a "Next Generation Core" for 2007, which is obviously K8L (and the whole article is about it).
For 2008, only a "Core Update" is mentioned, which does not sound like a complete core redesign to me.



Does it have to? Who are you? (Not trying to be funny)
July 4, 2006 2:39:14 PM

Quote:

I'm looking for the link. You make it sound like a physics problem would prevent them from ADDING ONE MORE DECODER.

Not at all.
I truly hope they'll add one decoder, or who knows, they might even do something completely different with their decoding engine.
Afterall they have twice as much fetched data to process.
Could it be the reverse hyperthreading? (they fetch twice as much data, then they see if they can dispatch it to 2 CPUs or only one)
My point is, that at the moment there is only speculation, as nothing has been disclosed concerning it, so i find it hard to predict what effect this will have on performance.
July 4, 2006 2:44:43 PM

Quote:

Does it have to? Who are you? (Not trying to be funny)

Who am i?
Just a "nobody" posting on an internet forum.
However, it is hard to explain that "Core Update" in the english language means "Complete Core Redesign" as the K10 is supposed to be.
Especially since they call K8L "Next Generation Core".
In my understanding, "Next Generation Core" means more than "Core Update" in a scale of improvements.
And we all know that K8L, though indeed a major improvement, is not considered to be a completely new architecture compared to K8.
July 4, 2006 2:51:58 PM

Quote:

I'm looking for the link. You make it sound like a physics problem would prevent them from ADDING ONE MORE DECODER.

Not at all.
I truly hope they'll add one decoder, or who knows, they might even do something completely different with their decoding engine.
Afterall they have twice as much fetched data to process.
Could it be the reverse hyperthreading? (they fetch twice as much data, then they see if they can dispatch it to 2 CPUs or only one)
My point is, that at the moment there is only speculation, as nothing has been disclosed concerning it, so i find it hard to predict what effect this will have on performance.


I understand. AMD is always tightlipped about new, unreleased products. Even if they weren't planning this anyway - if the K10 was cancelled in 2004 - it will still be at least 1.5X as fast as the K8 according to the specs.

1.5X or more will take them clock for clock higher than Core 2. There are a few Henri Richard articles on digitimes where he talk about most of this.

9inch nails postd a link to them here. go back about a week.
July 4, 2006 3:03:25 PM

Sure it will, only a bit less than Intel's then current releases! :wink:
July 4, 2006 3:50:11 PM

Quote:

Does it have to? Who are you? (Not trying to be funny)

Who am i?
Just a "nobody" posting on an internet forum.
However, it is hard to explain that "Core Update" in the english language means "Complete Core Redesign" as the K10 is supposed to be.
Especially since they call K8L "Next Generation Core".
In my understanding, "Next Generation Core" means more than "Core Update" in a scale of improvements.
And we all know that K8L, though indeed a major improvement, is not considered to be a completely new architecture compared to K8.

You are now a somebody, with that correct post
July 4, 2006 5:06:15 PM

Quote:

Does it have to? Who are you? (Not trying to be funny)

Who am i?
Just a "nobody" posting on an internet forum.
However, it is hard to explain that "Core Update" in the english language means "Complete Core Redesign" as the K10 is supposed to be.
Especially since they call K8L "Next Generation Core".
In my understanding, "Next Generation Core" means more than "Core Update" in a scale of improvements.
And we all know that K8L, though indeed a major improvement, is not considered to be a completely new architecture compared to K8.

I'm not on the inside but from the last interviews I read, 2008 will bring an entirely new architecture. There have been so many AMD interview lately I can't remember which ones but I believe it was the latest with Hector Ruiz.

ALso, I did a bit of investigation on the die shot from Anand's Analyst Day coverage and it looks like there are four decoders. Check the top left corner of the pic and there are FOUR large rectangles which look to be positioned where decoders are on K8.

After looking for the shot of Rev G, I found this interesting tidbit from Business Week Onine - should be reputable - and it says a few things I have noted.

Quote:
DiFranco channeled millions that had been earmarked for a branding campaign to stores, in the form of rebates, in-store promotions, employee training, and ad space in Sunday circulars. And he got lucky in December, when Intel stumbled into a parts shortage for its desktop PCs. When Intel earmarked key components for Dell, its closest PC partner, AMD quickly dispatched top salespeople to fill the void for irked competitors. Now AMD-based desktops dominate shelves at Best Buy (BBY ), Circuit City, and other stores.



The most interesting statement was this:

Quote:
The fired-up AMD team is girding, as well. AMD has spent millions of dollars on flashy billboards along Highway 101 in Silicon Valley and in New York's Times Square to convince corporate buyers that its server chips will still deliver the best bang for the buck. And in October it will roll out gamers' PC rigs that pack four processors onto one chip for lightning-fast performance. DiFranco is mum about what goals he will present at this June's AMD leadership retreat. A student of Sun Tzu's Art of War, he says cryptically that "you fight the battle you know you're going to win."
July 4, 2006 9:14:29 PM

Quote:
But K8L hs two FP units and double SSE FP @ 128.


*gasp* So does core you moron.

Quote:
4 complex decoders will increase their IPC by 25% or more.


Proof for four decoders please?

Quote:
Just admit it K8L will rock. It doesn't mean Intel sucks.


When did I say otherwise.

BM please stop posting your FUD or action will have to be taken.
July 4, 2006 9:17:02 PM

Quote:
1.5X K8 stupid.


Heres what you originally wrote dipsh!t.

Quote:
IF K8L lives up to the specs, it will eclipse Core 2, with 1.5x FP


K8 isn't even mentioned so STFU.
July 4, 2006 9:33:23 PM

Quote:
Hmmm.. yup could be, but Intel decided to fit Conroe with 3 simple decoders and 1 complex one.
Intel didnt decide to fit 3 complex decoders as AMD did, so i believe today's code is not composed of very long instructions.
When AMD fitted the K7 (then K8 ) with 3 complex decoders, it was more than 5 years ago, when legacy code still had its importance.
But then again, this is all speculation.


Whilst the simple decoders are simple by name they are far from it.
July 4, 2006 10:11:40 PM

Quote:
BM please stop posting your FUD or action will have to be taken.

You are very kind asking him to.....are you serious?
He will stop only over his dead fat body
July 4, 2006 11:36:08 PM

Quote:
But K8L hs two FP units and double SSE FP @ 128.


*gasp* So does core you moron.

Quote:
4 complex decoders will increase their IPC by 25% or more.


Proof for four decoders please?

Quote:
Just admit it K8L will rock. It doesn't mean Intel sucks.


When did I say otherwise.

BM please stop posting your FUD or action will have to be taken.


Take your pathetic one-liners and go. You are no better han anyone else. Does that mean your'e gonna tell your mommy on me?

Why would they add prefetch with the same amount of decoders?


No I get it you're going to report me for hurting oo wittle feewings.
July 4, 2006 11:37:40 PM

Quote:
Hmmm.. yup could be, but Intel decided to fit Conroe with 3 simple decoders and 1 complex one.
Intel didnt decide to fit 3 complex decoders as AMD did, so i believe today's code is not composed of very long instructions.
When AMD fitted the K7 (then K8 ) with 3 complex decoders, it was more than 5 years ago, when legacy code still had its importance.
But then again, this is all speculation.


Whilst the simple decoders are simple by name they are far from it.


They can get away with this because of micro ops fusion.
July 4, 2006 11:39:44 PM

Quote:
BM please stop posting your FUD or action will have to be taken.

You are very kind asking him to.....are you serious?
He will stop only over his dead fat body


It's funny how the links I post are ignored unless you can find a little disclaimer that disagrees. I try to preface my statements as to not soun dlike I know everything. You all get mad because you can't play super Intel fan boy with me.
July 4, 2006 11:57:32 PM

Quote:
with 1.5x FP


No.

Hmm...
K8L will be able to execute 4 FPU DP (64bit) operations per cycle (not counting load/store), that's 2x the performance of K8.
I don't remember Core having such a performance increase (i'm talking about FPU ops, not SSE FP ops), but i might be mistaken.


Quote:

4 decoders


No.
"Hmm..." again.
In fact, all it has been declared, is that K8L will be able to FETCH 32byte per clock instead of 16.
Now, this could either mean that K8L will be able to fetch and decode *very* long x86 instructions (though this is unlikely, as most of these instructions are legacy/unused in modern code) or that it will be able to decode more than 3 instructions per clock.
Though, this is still only speculation though.

However, i'm skeptical toward these "K10 in 2008" rumors.
Sure this was scheduled to happen, but i've seen only very old articles (1 year old or more) saying so.
In the latest AMD roadmap, according to the Anandtech article quoted by BaronMatrix, AMD speaks about "core update" in 2008.
That doesn't sound like a completely new core architecture, as K10 was supposed to be.
Also AMD has recently spoken about an "evolutionary, not revolutionary" approach..

First things first the K8L is on paper and poorly done CAD images. Secondly Core 2 can and does do 1 "complete" FPU INT SSE operation per cycle, as per how you believe the K8L is capable of doubling that is remarkable.

For the record Core 2 can commit resources for 4 full 32bit operations or 4 plus 1 SSE operations pushing for 5 but that is under very ideal conditions.

If its true the K8L can fetch 32byte stacks that’s great but with regards to the fact they have 64k of L1 Data and Instruction cache, seems pretty pointless when they should be aiming for a 100% L1 fill per cycle similar to Intel’s approach with the Core 2 uArch.
!