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Is SOI an issue with AMD's 65nm shrink?

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July 15, 2006 5:07:42 PM

I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?
July 15, 2006 5:31:32 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?



I doubt that there are any problems. Wall St doesn't like surprises. Ask Steve Ballmer. AMD was forthcoming about their slight Q2 dip.
July 15, 2006 5:36:43 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?


SOI in and of itself is part of the equation --- their real problems are in my opinion.

a) Stress memorization
b) embedded SiGe
c) Dual stress memorization
d) Strained SOI

It is complicating the complicated even further --- this what I don't understand about the giddiness of all this 40% stuff earlier on and the litany of process techs. people are soooooo excited about when AMD makes press releases about this stuff.

The glossy-eyed followers who drool over such technical sounding stuff think wow --- 4 stressors.

4 Stressors just to get to within 10% of Intel's tranistor performance is a lot of engineering (and variability) to make it work. Of these stressors, 3 are new to AMD. I am not buying AMD's claims that yields are hitting milestones, if they are then their milestones are setting low standards (in my opinion).

Jack

Jack, I understand what b&d are, but what's a&c? I guess it has something to do with a certain layer cracking, but why is it an issue?
Related resources
July 15, 2006 5:41:48 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?



I doubt that there are any problems. Wall St doesn't like surprises. Ask Steve Ballmer. AMD was forthcoming about their slight Q2 dip.

Well then if they have no problems then why haven't we seen any 65nm parts from them?
July 15, 2006 5:51:43 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?


SOI in and of itself is part of the equation --- their real problems are in my opinion.

a) Stress memorization
b) embedded SiGe
c) Dual stress memorization
d) Strained SOI

It is complicating the complicated even further --- this what I don't understand about the giddiness of all this 40% stuff earlier on and the litany of process techs. people are soooooo excited about when AMD makes press releases about this stuff.

The glossy-eyed followers who drool over such technical sounding stuff think wow --- 4 stressors.

4 Stressors just to get to within 10% of Intel's tranistor performance is a lot of engineering (and variability) to make it work. Of these stressors, 3 are new to AMD. I am not buying AMD's claims that yields are hitting milestones, if they are then their milestones are setting low standards (in my opinion).

Jack

Jack, I understand what b&d are, but what's a&c? I guess it has something to do with a certain layer cracking, but why is it an issue?


a) is a technique where special masks are applied so that when the mask is removed it maintains the shape of the gate structure.

c) is a SiGe technique that allows AMD to add more "strength" to the drains - I believe - which lowers the leakage current as you switch on and off.

I guess you could Google it like Jack would have to.
July 15, 2006 5:54:46 PM

OK...I could of googled it, but I wanted to know why he thought it was an issue.
July 15, 2006 6:07:17 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?



I doubt that there are any problems. Wall St doesn't like surprises. Ask Steve Ballmer. AMD was forthcoming about their slight Q2 dip.

Well then if they have no problems then why haven't we seen any 65nm parts from them?


What do you want to see? Intel has 12 Fabs, AMD has 3. Of ocurse they won't be liberally sprinkling these out yet. They aren't due until Dec. Core 2 was due in June and samples popped up in Apr. I fthey don't have them in Oct, I would think there maybe a problem. Jack I believe posted there qualification schedule.
July 15, 2006 6:12:09 PM

Quote:
OK...I could of googled it, but I wanted to know why he thought it was an issue.


So I will give you my thoughts on why it is causing problems:

a) Stress memorization
This is actually a pretty straight forward technique -- unlike BM explanation, it does not take highly specific masks to accomplish this -- depending on the stressing you are doing, it is as simple as covering up all the NMOS and exposing PMOS and stress memorizing a compressive film or covering all the PMOS and stress memorizing a tensile film for NMOS perfomrance. The problem is, adding any new step into the series of steps creates opportinities for screwing it up :) , i.e. random defects due to particles, misalignment of mask (registrations), etc. etc. The other hard part is the SOI interaction with the memorization itself.

Due to the thermal conductivities of SOI in the buried layers, the anneal and thermal profiles in the sub-surface region are significantly different than in bulk -- so if not done well, or correctly, you can screw up all your other implants. This will actually degrade performance.

c) Dual stress liner -- similar argument as a above, it also significantly increases cost by having to mask 1/2 our wafer to do one layer and mask the other half to do the other. In contrast to Intel, they use one stress liner and then have engineered other stress techniques to over compensate over the other device (quite brilliant, and cost effective actually).

AMD's major head ache is coming with the other two, SiGe in my opinion -- first, there are rumors that the strained SOI is not working well at all (started by the Inquirer of all places) it is a difficult thing to do no doubt. The second is the embedded SiGe -- AMD already has problems with sub-surface dislocations beneath the source and drain evident from the SEM and TEM data that can be found on the web (a major reason why I do not purchase AMD processors :)  )... adding a high stress but very fragile SiGe film will only make that worst.

In short, to implement all the stuff they need to get performance up they open themselves up to new defect modes that can cause major yield fall out. Basically, I would not be surprised if they release significantly slower parts and disclose that they have dropped the SiGe ideas for now with the concept of adding them back in at a later date.

Jack

AMD is not counting on this for clock speed increase so they have less "stress" on them. I have been using my 4400+ constantly since last Oct. It may have been off for 20 minutes (not including standby). I could say that I don't buy Intel because IBM is on the same schedule and they are responsible for Power5.

If they maintain their current speeds as the process matures I don't see yields going down significantly from the current gen techniques. Didn't you post their qualification schedule as ending in Nov?
July 15, 2006 6:15:52 PM

Quote:
OK...I could of googled it, but I wanted to know why he thought it was an issue.


So I will give you my thoughts on why it is causing problems:

a) Stress memorization
This is actually a pretty straight forward technique -- unlike BM explanation, it does not take highly specific masks to accomplish this -- depending on the stressing you are doing, it is as simple as covering up all the NMOS and exposing PMOS and stress memorizing a compressive film or covering all the PMOS and stress memorizing a tensile film for NMOS perfomrance. The problem is, adding any new step into the series of steps creates opportinities for screwing it up :) , i.e. random defects due to particles, misalignment of mask (registrations), etc. etc. The other hard part is the SOI interaction with the memorization itself.

Due to the thermal conductivities of SOI in the buried layers, the anneal and thermal profiles in the sub-surface region are significantly different than in bulk -- so if not done well, or correctly, you can screw up all your other implants. This will actually degrade performance.

c) Dual stress liner -- similar argument as a above, it also significantly increases cost by having to mask 1/2 our wafer to do one layer and mask the other half to do the other. In contrast to Intel, they use one stress liner and then have engineered other stress techniques to over compensate over the other device (quite brilliant, and cost effective actually).

AMD's major head ache is coming with the other two, SiGe in my opinion -- first, there are rumors that the strained SOI is not working well at all (started by the Inquirer of all places) it is a difficult thing to do no doubt. The second is the embedded SiGe -- AMD already has problems with sub-surface dislocations beneath the source and drain evident from the SEM and TEM data that can be found on the web (a major reason why I do not purchase AMD processors :)  )... adding a high stress but very fragile SiGe film will only make that worst.

In short, to implement all the stuff they need to get performance up they open themselves up to new defect modes that can cause major yield fall out. Basically, I would not be surprised if they release significantly slower parts and disclose that they have dropped the SiGe ideas for now with the concept of adding them back in at a later date.

Jack

Jack, are both SOI and SiGe both used for current leakage? I am aware that they use SOI on 90nm but do they also use SiGe? One last thing I think I read somewhere that SOI is difficult to implement under 90nm, any insight into this?
July 15, 2006 6:19:04 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?



I doubt that there are any problems. Wall St doesn't like surprises. Ask Steve Ballmer. AMD was forthcoming about their slight Q2 dip.

Well then if they have no problems then why haven't we seen any 65nm parts from them?


What do you want to see? Intel has 12 Fabs, AMD has 3. Of ocurse they won't be liberally sprinkling these out yet. They aren't due until Dec. Core 2 was due in June and samples popped up in Apr. I fthey don't have them in Oct, I would think there maybe a problem. Jack I believe posted there qualification schedule.

Intel has 3 Fabs at 65nm pumping out Core 2's, while AMD has 2 Fabs and 1 on the drawing board.
July 15, 2006 6:21:41 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?



I doubt that there are any problems. Wall St doesn't like surprises. Ask Steve Ballmer. AMD was forthcoming about their slight Q2 dip.

Well then if they have no problems then why haven't we seen any 65nm parts from them?


What do you want to see? Intel has 12 Fabs, AMD has 3. Of ocurse they won't be liberally sprinkling these out yet. They aren't due until Dec. Core 2 was due in June and samples popped up in Apr. I fthey don't have them in Oct, I would think there maybe a problem. Jack I believe posted there qualification schedule.

What does fab capacity have to do with R&D?
July 15, 2006 6:29:21 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?


SOI in and of itself is part of the equation --- their real problems are in my opinion.

a) Stress memorization
b) embedded SiGe
c) Dual stress memorization
d) Strained SOI

It is complicating the complicated even further --- this what I don't understand about the giddiness of all this 40% stuff earlier on and the litany of process techs. people are soooooo excited about when AMD makes press releases about this stuff.

The glossy-eyed followers who drool over such technical sounding stuff think wow --- 4 stressors.

4 Stressors just to get to within 10% of Intel's tranistor performance is a lot of engineering (and variability) to make it work. Of these stressors, 3 are new to AMD. I am not buying AMD's claims that yields are hitting milestones, if they are then their milestones are setting low standards (in my opinion).

Jack

Jack, I understand what b&d are, but what's a&c? I guess it has something to do with a certain layer cracking, but why is it an issue?


a) is a technique where special masks are applied so that when the mask is removed it maintains the shape of the gate structure.

c) is a SiGe technique that allows AMD to add more "strength" to the drains - I believe - which lowers the leakage current as you switch on and off.

I guess you could Google it like Jack would have to.

A) This is utterly incorrect.
C) Is again utterly incorrect.


Not accordign to this


Quote:
One of those methods is called strained silicon. When certain materials are laid atop the silicon substrate on which transistors are built, the atoms in those substances align with each other, compressing or stretching the silicon. Positive transistors run better when they have been compressed, while negative transistors benefit from being stretched. IBM and AMD introduced Dual Stress Liner technology last year that allowed both types of strain to exist side-by-side on a chip.

The companies have developed two new methods of straining transistors that build on the Dual Stress Liner (DSL) technique to improve the performance of 65nm processors, said John Pellerin, director of logic technology development at IBM. The label of 65nm manufacturing technology corresponds to the average size of features on the chips, in this case a reduction from the current 90nm generation of chip-making technology.

The first method, known as stress memorization technology, improves the performance of negative transistors by adding a thin film of silicon nitride to a negative transistor, causing the atoms to move, and then removing that film, Pellerin said. The atoms “memorize” their position and stay in place after the film is removed, hence the name, he said.

The second method involves adding silicon germanium to positive transistors, Bronner said. The silicon germanium is essentially grown right next to the transistor gate, compressing that channel. The companies used to consider silicon germanium a difficult material to use in high-volume chip manufacturing, but they became accustomed to the use of the material during their collaboration, he said.




Linkage!


Or this

Quote:
The companies announced that they have successfully combined embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers, resulting in a 40 percent increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation.

The new process technologies reduce interconnect delay through the use of lower dielectric constant (lower-K) insulators, which can improve overall product performance and lower power consumption. In addition, the new technologies have shown ability to be manufactured at the 65nm generation and scaleable for use in future generations.

“Our joint work on developing advanced process technologies continues to ensure we can create and provide the highest performance, lowest power processors on the market,” said Nick Kepler, vice president of logic technology development at AMD. “Yet again, we can add another achievement to our list of successes that demonstrate how shared expertise and skills can result in overcoming roadblocks and creating more valuable innovations for customers.”
July 15, 2006 6:52:24 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?


SOI in and of itself is part of the equation --- their real problems are in my opinion.

a) Stress memorization
b) embedded SiGe
c) Dual stress memorization
d) Strained SOI

It is complicating the complicated even further --- this what I don't understand about the giddiness of all this 40% stuff earlier on and the litany of process techs. people are soooooo excited about when AMD makes press releases about this stuff.

The glossy-eyed followers who drool over such technical sounding stuff think wow --- 4 stressors.

4 Stressors just to get to within 10% of Intel's tranistor performance is a lot of engineering (and variability) to make it work. Of these stressors, 3 are new to AMD. I am not buying AMD's claims that yields are hitting milestones, if they are then their milestones are setting low standards (in my opinion).

Jack

Jack, I understand what b&d are, but what's a&c? I guess it has something to do with a certain layer cracking, but why is it an issue?


a) is a technique where special masks are applied so that when the mask is removed it maintains the shape of the gate structure.

c) is a SiGe technique that allows AMD to add more "strength" to the drains - I believe - which lowers the leakage current as you switch on and off.

I guess you could Google it like Jack would have to.

A) This is utterly incorrect.
C) Is again utterly incorrect.


Not accordign to this


Quote:
One of those methods is called strained silicon. When certain materials are laid atop the silicon substrate on which transistors are built, the atoms in those substances align with each other, compressing or stretching the silicon. Positive transistors run better when they have been compressed, while negative transistors benefit from being stretched. IBM and AMD introduced Dual Stress Liner technology last year that allowed both types of strain to exist side-by-side on a chip.

The companies have developed two new methods of straining transistors that build on the Dual Stress Liner (DSL) technique to improve the performance of 65nm processors, said John Pellerin, director of logic technology development at IBM. The label of 65nm manufacturing technology corresponds to the average size of features on the chips, in this case a reduction from the current 90nm generation of chip-making technology.

The first method, known as stress memorization technology, improves the performance of negative transistors by adding a thin film of silicon nitride to a negative transistor, causing the atoms to move, and then removing that film, Pellerin said. The atoms “memorize” their position and stay in place after the film is removed, hence the name, he said.

The second method involves adding silicon germanium to positive transistors, Bronner said. The silicon germanium is essentially grown right next to the transistor gate, compressing that channel. The companies used to consider silicon germanium a difficult material to use in high-volume chip manufacturing, but they became accustomed to the use of the material during their collaboration, he said.




Linkage!


Or this

Quote:
The companies announced that they have successfully combined embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers, resulting in a 40 percent increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation.

The new process technologies reduce interconnect delay through the use of lower dielectric constant (lower-K) insulators, which can improve overall product performance and lower power consumption. In addition, the new technologies have shown ability to be manufactured at the 65nm generation and scaleable for use in future generations.

“Our joint work on developing advanced process technologies continues to ensure we can create and provide the highest performance, lowest power processors on the market,” said Nick Kepler, vice president of logic technology development at AMD. “Yet again, we can add another achievement to our list of successes that demonstrate how shared expertise and skills can result in overcoming roadblocks and creating more valuable innovations for customers.”


Dude-- what you stated and what you quoted are two different things, if you read back through the posting, everyting you quote was stipulated in my responses. Second, those are dummy macworld reporters who basically know how to spell SiGe --- they are parroting press release notes. I provided the technical jounal articles that provide the actual data and physics of the methods.

You state:
Quote:
a) is a technique where special masks are applied so that when the mask is removed it maintains the shape of the gate structure.
How does this correlate to your quote above.... what exactly is that thing which maintains the gate structure ???? What the hell are you talking about. A special mask? What litho do they do???? You spewed from your bowels utter nonsense.

The next you state:
Quote:
c) is a SiGe technique that allows AMD to add more "strength" to the drains - I believe - which lowers the leakage current as you switch on and off.
Which again, has nothing to do with leakage -- embedding SiGe is a method to stress PMOS (which the authors of your quotes novicely and incorrectly call positive and negative transistors). Again, your second statement demonstrates complete ignorance of a topic you are trying to discuss. Where in your quote does it talk about strength?? What is strength??? I can only assume you mean stress, which physically is also incorrect --- the right term is STRAIN. But the industry has settled on stress -- ok so be it, they are inter-related as stress is the property of the film and strain is the deformation of the bulk due to the stress, make no mistake it is the strain on the channel that is in important here.

Now Baron, you can continue this silly attempt to display some knowledge but on this topic I will bury you in a heartbeat.

Jack

Word.
July 15, 2006 7:00:05 PM

Quote:

AMD is not counting on this for clock speed increase so they have less "stress" on them. I have been using my 4400+ constantly since last Oct. It may have been off for 20 minutes (not including standby). I could say that I don't buy Intel because IBM is on the same schedule and they are responsible for Power5.

If they maintain their current speeds as the process matures I don't see yields going down significantly from the current gen techniques. Didn't you post their qualification schedule as ending in Nov?


Are you kiddin'??? This was the thrust of their song and dance for performance improvement.

Please provide a link where AMD states they are not counting on stress engineering for clock speed.... the are not only counting on it, they are betting their future on it.



Show me where they say they are aiming for MUCH higher clock speeds. They will get speed increases from the shrink - not a lot - but the new techniques are more for power mgmt. If they get 20% icrease from the shrink, that's 20% of 3.0GHz (FX64). That's 700MHz plus which will take them to nearly 4GHz.

I thought they were counting on K8L?
July 15, 2006 7:07:00 PM

Quote:

Jack, are both SOI and SiGe both used for current leakage? I am aware that they use SOI on 90nm but do they also use SiGe? One last thing I think I read somewhere that SOI is difficult to implement under 90nm, any insight into this?


SOI is used for junction leakage and parasitic capacitance, it also aids in reducing short channel effects. You are correct, AMD suffered yield issues upon the first implementation run of SOI, Hector Ruiz actually had an analyst presentation that graphed out the defect counts before and after a 'fix'. Their fix was simply to screen and throw out bad wafers before they started. I will look up the link --- this is not an opinion, it is a fact. SOI is not a stressing technique, however due to mismatch of materials in the buried oxide does induce some amount of stress but the nature of the wafer precludes actually engineering that stress until recently. I.e. it was not a stress knob to turn up or down. Strained SOI is either a graded SiGe film overlayer between the oxide and Si surface or it is 'stress memorized' by cleaving back from a SiGe sacrificial layer in the production of the SOI wafer. IBM has a nice cartoon of the latter:
http://domino.watson.ibm.com/comm/pr.nsf/pages/rscd.cmo...

SiGe is used for stress to 'push' against the channel. Ge, being larger atomically than Si, when mixed as an allow has lower density and a larger unit cell volume. When buried in the source/drain region creates a compressive stress in the silicon region that makes up the channel, this in turn increases electron mobility and drives up the Idsat (i.e. speeds up the transistor).

Jack


Dufus, my only mistake was saying "drain" instead of channel. Compressing the channel strengthens it and allows for faster switching with less laekage.

Your IBM leak says nearly EXACTLY that. A "special mask" is used to "memorize" the shape of the gate after it is removed.

You are the grade school idiot. Unless, as you like to say to me, you are now a CPU engineer and not just a guy with no life who searches for links all day.

I can read too.
July 15, 2006 7:34:52 PM

Well, you guys confused the heck out of me for most of this thread. Either your written language isn't English or I'm just not that smart.

I got the impression from general research and development, that one small snag could hold a project up weeks if not months. I imagine SOI could be part of the hold up, but then again so could getting anything in the production equipment and process, ready and running with sufficient success they can think about supplying a hungry market.

I can't imagine AMD are sitting on their hands watching ABC, 65nm will be here the second it's viable. Speculation on why it isn't yet is just that, speculation. I have my own speculation but it's probably as valid as a pre-school childs attempt at differential calculus - which by the way is, that 65nm on its own isn't going to generate a big enough difference to justify a completely new process, socket, and everything else that it will require to get it to market. They would be in my humble oppinion, be trying to get as many new features to go with 65nm so they can, in an attempt to compete with the feature rich new archetecture on the block.

That would be my guess, as they wouldn't want to release something new that didn't match up to Conro.

Now guys, isn't that a lot more friendly thn saying all that in-depth technical mumbo-jumbo that no one really understands? :)  *said in a nice, friendly, joking way*
July 15, 2006 8:12:22 PM

Quote:

Jack, are both SOI and SiGe both used for current leakage? I am aware that they use SOI on 90nm but do they also use SiGe? One last thing I think I read somewhere that SOI is difficult to implement under 90nm, any insight into this?


SOI is used for junction leakage and parasitic capacitance, it also aids in reducing short channel effects. You are correct, AMD suffered yield issues upon the first implementation run of SOI, Hector Ruiz actually had an analyst presentation that graphed out the defect counts before and after a 'fix'. Their fix was simply to screen and throw out bad wafers before they started. I will look up the link --- this is not an opinion, it is a fact. SOI is not a stressing technique, however due to mismatch of materials in the buried oxide does induce some amount of stress but the nature of the wafer precludes actually engineering that stress until recently. I.e. it was not a stress knob to turn up or down. Strained SOI is either a graded SiGe film overlayer between the oxide and Si surface or it is 'stress memorized' by cleaving back from a SiGe sacrificial layer in the production of the SOI wafer. IBM has a nice cartoon of the latter:
http://domino.watson.ibm.com/comm/pr.nsf/pages/rscd.cmo...

SiGe is used for stress to 'push' against the channel. Ge, being larger atomically than Si, when mixed as an allow has lower density and a larger unit cell volume. When buried in the source/drain region creates a compressive stress in the silicon region that makes up the channel, this in turn increases electron mobility and drives up the Idsat (i.e. speeds up the transistor).

Jack


Dufus, my only mistake was saying "drain" instead of channel. Compressing the channel strengthens it and allows for faster switching with less laekage.

Your IBM leak says nearly EXACTLY that. A "special mask" is used to "memorize" the shape of the gate after it is removed.

You are the grade school idiot. Unless, as you like to say to me, you are now a CPU engineer and not just a guy with no life who searches for links all day.

I can read too.

Strengthen, what is strengthen???? Give me the units for strengthen.... Strain, which is what you mean, is deminsionless stress is Dyne/cm^2 which induces strain.

You may know how to read, but you obviously do not understand what you read.

And what is it about the AMD fanantic, they naturally assume that any techncial reference is googled.... this get's pulled on me everytime :)  It's laughable.

Baron, I have two PhDs, one in chemistry and one in physics, I recieved my degrees from UT Austin, working in the Center for Sysnthese, Growth, and Analsyis of Electronic Matrials, an NSF fundeded science and technology center... SiGe was one topic used in my dissertation, SiC grown and analysis was another. Nothing you quote or say has any true technical merit at a level of understanding necessary to make conclusions they way you do.

My specialty is solid state physics and chemistry. Would you liked to be schooled on exactly what crappola you are spewing?



So where are the pics of your degrees? You can tell me anything. I quoted fuzzy logic as an ME and what was your sorry a s s reaction? I quoted that I worked five years at MS, what was your sorry a s s reaction.

Face it, school has not helped you. I use simple terms because who understands real CPU speak?

When I was in college my Sr Design project was an automated start stop mechanism for a vertical Axis Wind Turbine so I know a little bit about electronics.

You are the one who speaks so matter of factly. Have you ever seen the inside of a clean room?
July 15, 2006 8:27:45 PM

Quote:

Jack, are both SOI and SiGe both used for current leakage? I am aware that they use SOI on 90nm but do they also use SiGe? One last thing I think I read somewhere that SOI is difficult to implement under 90nm, any insight into this?


SOI is used for junction leakage and parasitic capacitance, it also aids in reducing short channel effects. You are correct, AMD suffered yield issues upon the first implementation run of SOI, Hector Ruiz actually had an analyst presentation that graphed out the defect counts before and after a 'fix'. Their fix was simply to screen and throw out bad wafers before they started. I will look up the link --- this is not an opinion, it is a fact. SOI is not a stressing technique, however due to mismatch of materials in the buried oxide does induce some amount of stress but the nature of the wafer precludes actually engineering that stress until recently. I.e. it was not a stress knob to turn up or down. Strained SOI is either a graded SiGe film overlayer between the oxide and Si surface or it is 'stress memorized' by cleaving back from a SiGe sacrificial layer in the production of the SOI wafer. IBM has a nice cartoon of the latter:
http://domino.watson.ibm.com/comm/pr.nsf/pages/rscd.cmo...

SiGe is used for stress to 'push' against the channel. Ge, being larger atomically than Si, when mixed as an allow has lower density and a larger unit cell volume. When buried in the source/drain region creates a compressive stress in the silicon region that makes up the channel, this in turn increases electron mobility and drives up the Idsat (i.e. speeds up the transistor).

Jack


Dufus, my only mistake was saying "drain" instead of channel. Compressing the channel strengthens it and allows for faster switching with less laekage.

Your IBM leak says nearly EXACTLY that. A "special mask" is used to "memorize" the shape of the gate after it is removed.

You are the grade school idiot. Unless, as you like to say to me, you are now a CPU engineer and not just a guy with no life who searches for links all day.

I can read too.

Strengthen, what is strengthen???? Give me the units for strengthen.... Strain, which is what you mean, is deminsionless stress is Dyne/cm^2 which induces strain.

You may know how to read, but you obviously do not understand what you read.

And what is it about the AMD fanantic, they naturally assume that any techncial reference is googled.... this get's pulled on me everytime :)  It's laughable.

Baron, I have two PhDs, one in chemistry and one in physics, I recieved my degrees from UT Austin, working in the Center for Sysnthese, Growth, and Analsyis of Electronic Matrials, an NSF fundeded science and technology center... SiGe was one topic used in my dissertation, SiC grown and analysis was another. Nothing you quote or say has any true technical merit at a level of understanding necessary to make conclusions they way you do.

My specialty is solid state physics and chemistry. Would you liked to be schooled on exactly what crappola you are spewing?



So where are the pics of your degrees? You can tell me anything. I quoted fuzzy logic as an ME and what was your sorry a s s reaction? I quoted that I worked five years at MS, what was your sorry a s s reaction.

Face it, school has not helped you. I use simple terms because who understands real CPU speak?

When I was in college my Sr Design project was an automated start stop mechanism for a vertical Axis Wind Turbine so I know a little bit about electronics.

You are the one who speaks so matter of factly. Have you ever seen the inside of a clean room?

Poser.
You Haven't Even Left Your Parents Basement Yet So Shut The Hell Up!
July 15, 2006 8:42:01 PM

Quote:
You are the one who speaks so matter of factly. Have you ever seen the inside of a clean room?


As a matter of fact I have.

Quote:
Face it, school has not helped you. I use simple terms because who understands real CPU speak?


You use simple terms because you don't understand anything.

Quote:
When I was in college my Sr Design project was an automated start stop mechanism for a vertical Axis Wind Turbine so I know a little bit about electronics.


You went to college, I'm shocked... my undergraduate degree Sr project was Hartree-Fock calcuations for the Molecular Obitals of AlF3. So I believe I know a little about chemsitry.

jack owned BM...

lolz...


oops do not pissed me... im am now inside intel's clean room... o_0
July 15, 2006 8:45:33 PM

Quote:
You are the one who speaks so matter of factly. Have you ever seen the inside of a clean room?


As a matter of fact I have.

Quote:
Face it, school has not helped you. I use simple terms because who understands real CPU speak?


You use simple terms because you don't understand anything.

Quote:
When I was in college my Sr Design project was an automated start stop mechanism for a vertical Axis Wind Turbine so I know a little bit about electronics.


You went to college, I'm shocked... my undergraduate degree Sr project was Hartree-Fock calcuations for the Molecular Obitals of AlF3. So I believe I know a little about chemsitry.

So you're like one of those guys who does lots of math and only produces used up paper?
July 15, 2006 8:48:10 PM

Quote:

Jack, are both SOI and SiGe both used for current leakage? I am aware that they use SOI on 90nm but do they also use SiGe? One last thing I think I read somewhere that SOI is difficult to implement under 90nm, any insight into this?


Oh, I did not answer you second question --- SiGe is new to AMD in the 65 nm process, SiGe is not used in the 90 nm process. For a good review of the differences between the AMD/Intel 90 nm technology nodes, i found this review with cross-sectional SEM phototraphs of the transistors:

http://www.chipworks.com/resources/whitepapers/3.4a_Jam...

(I have posted this link often -- so many forum members may be very familiar with it).

One point to note, that even though AMD quotes a node, their Lg dimension rarely hits the ITRS roadmap --- furthermore, it is the largest on average in the MPU segment of the process. I.e. read -- not very good.

Jack

Thanks Jack.
July 15, 2006 8:50:45 PM

Quote:
One point to note, that even though AMD quotes a node, their Lg dimension rarely hits the ITRS roadmap --- furthermore, it is the largest on average in the MPU segment of the process. I.e. read -- not very good.



But yet still good enough to own the 4Way space.
July 15, 2006 8:51:22 PM

LMAO give up moron.
July 15, 2006 8:54:11 PM

Quote:
You are the one who speaks so matter of factly. Have you ever seen the inside of a clean room?


As a matter of fact I have.

Quote:
Face it, school has not helped you. I use simple terms because who understands real CPU speak?


You use simple terms because you don't understand anything.

Quote:
When I was in college my Sr Design project was an automated start stop mechanism for a vertical Axis Wind Turbine so I know a little bit about electronics.


You went to college, I'm shocked... my undergraduate degree Sr project was Hartree-Fock calcuations for the Molecular Obitals of AlF3. So I believe I know a little about chemsitry.

So you're like one of those guys who does lots of math and only produces used up paper?

I was an experimentalist in grad school.


So post your degree. Unless they don't allow that in the Internet Cafe for the homeless.
July 15, 2006 9:10:16 PM

Hahaha, nice work moron. I'll just use all the calls they used against me on them! Brillant strategy.
July 15, 2006 9:20:59 PM

I'm kinda dissapointed, I thought I'd try and post something to the best of my ability to contribute to the conversation, and all you guys can do is flame each other and ignored the comments all together!

Save the school boy one-up-mans-ship for messanger, leave that out of your posts and debate like adults. I'm surprised the MOD's here continue to allow flame posts and simply just dont lock threads on the spot.
July 15, 2006 9:39:22 PM

Quote:
I'm kinda dissapointed, I thought I'd try and post something to the best of my ability to contribute to the conversation, and all you guys can do is flame each other and ignored the comments all together!

Save the school boy one-up-mans-ship for messanger, leave that out of your posts and debate like adults. I'm surprised the MOD's here continue to allow flame posts and simply just dont lock threads on the spot.



I apologize. Sometimes I play with my pets too much. They usually lock them when someone complains. I admit I was trying to answer the person's question and was toild I didn't use th eright vocab and was therefore wrong.


As afr your comments, AMD has demoed the chip for a few reporters in Dresden, Germany. Problems can cause delays especially with new techniwues and can delay them, but AMD is going into validation for the X2 chips due out in Dec(OEM)/Jan(Retail). ALso IBM is on the same schedule as AMD so they can work together toiron out any problems before they delay production. No one is perfect but AMD has been executing nearly flawlessly with K8.

Technical matters aside they have investors and Wall St to answer to and are usually forthcoming in their schedule assessments. IBM/Chartered/AMD are all working together on 65nm and 45nm. I think they will get it out. AMDs APM equipment is pretty good and is installed for 90nm at Chartered and Chartered is also due for Q107 @ 65nm.


AMD has to smart because they are smaller. That means not attempting too much alone. I'm sure Dell maybe one of the OEMs set to get 65nm X2 in Dec. Heck they may get most or all.
July 15, 2006 10:02:12 PM

So what you are saying is, AMD are going ahead with a new 65nm line of basicaly the same chips? I really don't understand this - even if they push a few hundred extra Mhz out of each CPU and lower the price, it's not really going to be enough to take back their crown.

Hopefully that's not the case and AMD can hit back a lot harder.

Oh and I agree, AMD has to be a lot smarter than Intel, in fact, because of marketing stratagies and product placement, I think AMD has to have a far cheaper/performance or far better product
July 15, 2006 10:19:24 PM

They don't have to regain the crown all at once. They just need to stay competitive and power friendly.

They are due to relase quad for 65nm and are even SUPPOSEDLY updating the core in the form of K8L for servers.

As I said they can't afford to just jump to a new architecture. It took Intel 2-3 years to catch up in desktop/server. You can see is the Anand tests that at real gameplay resolutions they offer a competitive product.

People who say an 805D at 3.anything GHz is something more than the 965EE in tests is smoking crack. I appreciate the tests that show ho wmuch CPU power Core 2 has but those comparisons don't tell me what my resolution would play at with the various GPU setups available.


The 5000+ beats the 965EE so AMD is in a better position since they don't have to sell against themselves. Almost ALL of 939 and single core chips have been cancelled. Less products means fewer buying decisions and more sales.

With 65nm there can be up to 6000+ (3.6GHz) which is 1GHz or the 20-30% increase it is assumed they can get. But again they will do more power tuning than speeding up. Especially for businesses with 24/7 wksta.


Then the lesson can be applied to the quad K8, BullDozer and K8L server. They have often said they are following an evolutionary and not revolutionary course.
July 15, 2006 10:34:56 PM

Maybe I'm just paranoid because I am so used to AMD cracking out fantastic products and becoming what I percieved to be the ultimate producer of CPU's. In fact, when I built systems over the previous few years, I never once looked more than a few times at possible Intel solutions. It always ended up being AMD.

Now, the next system thats going to be built, has to be Conro based around the 6600, and I wonder how long these new developments from AMD are going to take. Perhaps it will only be a good thing though, lower prices, more fight back from AMD, time will tell, just hope its not too long.
July 15, 2006 10:59:33 PM

Quote:
Maybe I'm just paranoid because I am so used to AMD cracking out fantastic products and becoming what I percieved to be the ultimate producer of CPU's. In fact, when I built systems over the previous few years, I never once looked more than a few times at possible Intel solutions. It always ended up being AMD.

Now, the next system thats going to be built, has to be Conro based around the 6600, and I wonder how long these new developments from AMD are going to take. Perhaps it will only be a good thing though, lower prices, more fight back from AMD, time will tell, just hope its not too long.



I wil only say that I am confident in AMDs execution on everything talked abotu at Analysts Day. We are talking 4 months for 65nm, 6 months for K8L samples and 2-3 months for 4x4. I hope AMD takes this across teh whole line. Especially since the FX wil always differnentiate itself from the X2s.

I just liek AMDs platform approach vs. Intel's CPU approach. As I've said the onley platform additions from Intel in 5 years has been chipset wireless.
WOW.
AMD has introduced mainstream 64 bit, HTX, cHT, IMC, Torrenza (not released), and 4x4 (not released). That is what a modern CPU company should be doing.


Everyone knows that Intel will only be 25-40% Core 2 in Q107 and that includes Woodcrest, Merom, and Conroe. AMD will be 100% AM2, S1, and 1207. They have cancelled allfo the older chips and will stop amking them soon. Thsi frees up more space for new projects and more wafers. Thsi will enale them to tweak the AM2 process even more and by Q1, AM2 will be at Rev F3. I fyou look at Rev E form E2 - E6, there were both power improvements and perf improvements. I expect the same here and that those improvements will go into Rev G 65nm.


ALl tests show that AM2 gets a good deal more bandwidth from DDR2 800 and tweaking the process can help them use more of it. That in and of itself will give them increases just like with DDR (AMD pushed the speeds up to 600 and USED it all).


They have my confidence and my continued support.
July 15, 2006 11:06:12 PM

Quote:
Everyone knows that Intel will only be 25-40% Core 2 in Q107 and that includes Woodcrest, Merom, and Conroe.


BS its 70% for woodcrest, ~40% for conroe and no idea about merom.
July 15, 2006 11:15:50 PM

Quote:

Jack, are both SOI and SiGe both used for current leakage? I am aware that they use SOI on 90nm but do they also use SiGe? One last thing I think I read somewhere that SOI is difficult to implement under 90nm, any insight into this?


SOI is used for junction leakage and parasitic capacitance, it also aids in reducing short channel effects. You are correct, AMD suffered yield issues upon the first implementation run of SOI, Hector Ruiz actually had an analyst presentation that graphed out the defect counts before and after a 'fix'. Their fix was simply to screen and throw out bad wafers before they started. I will look up the link --- this is not an opinion, it is a fact. SOI is not a stressing technique, however due to mismatch of materials in the buried oxide does induce some amount of stress but the nature of the wafer precludes actually engineering that stress until recently. I.e. it was not a stress knob to turn up or down. Strained SOI is either a graded SiGe film overlayer between the oxide and Si surface or it is 'stress memorized' by cleaving back from a SiGe sacrificial layer in the production of the SOI wafer. IBM has a nice cartoon of the latter:
http://domino.watson.ibm.com/comm/pr.nsf/pages/rscd.cmo...

SiGe is used for stress to 'push' against the channel. Ge, being larger atomically than Si, when mixed as an allow has lower density and a larger unit cell volume. When buried in the source/drain region creates a compressive stress in the silicon region that makes up the channel, this in turn increases electron mobility and drives up the Idsat (i.e. speeds up the transistor).

Jack


Dufus, my only mistake was saying "drain" instead of channel.

You have a lot of cred to call Jack that... :roll:
July 15, 2006 11:25:45 PM

BM, I too really like AMD's approach over the past few years. It allowed me to make some really good, reliable, cheap systems for people. I just dont see enough evidence AMD will come through with really competitive solutions early enough for my liking.

AM, can I have a link for that please, I'd like to see that out of interest. Thanks :) 
July 15, 2006 11:28:58 PM

Link.

Quote:
He said Intel will transform Xeon DP product line to Woodcrest to the tune of 75 per cent by Q4.
July 15, 2006 11:39:19 PM

Thank you, that makes sense, although it's not from the most reliable source on the net. Certainly sounds like they are trying to get all their "ducks in a row".
July 15, 2006 11:44:23 PM

Quote:
Everyone knows that Intel will only be 25-40% Core 2 in Q107 and that includes Woodcrest, Merom, and Conroe.


BS its 70% for woodcrest, ~40% for conroe and no idea about merom.

So you're saying that Tulsa will be selling like hotcakes or maybe Dempsey? How about 915, 925, etc.

Production is one thing OEM stock is another. They may have planned properly for stopping P4 production but at this point they can't stop making them. They haven't really talked about the schedule for ending P4 production and with Core Duo in Macs (it's said they will adopt 51xx), there will be a lot of non Core 2 in the channel until Q207 in my opinion. It maybe earlier if Intel has timing on their side.

AMD has 3 distinct product lines.
July 15, 2006 11:45:29 PM

Quote:
Everyone knows that Intel will only be 25-40% Core 2 in Q107 and that includes Woodcrest, Merom, and Conroe. AMD will be 100% AM2, S1, and 1207. They have cancelled allfo the older chips and will stop amking them soon. Thsi frees up more space for new projects and more wafers. Thsi will enale them to tweak the AM2 process even more and by Q1, AM2 will be at Rev F3. I fyou look at Rev E form E2 - E6, there were both power improvements and perf improvements. I expect the same here and that those improvements will go into Rev G 65nm.


That is awful for AMD to cancel all non-AM2 product lines! How could you admire a company for abandoning its loyal customers? Screw all socket 939 and 754 customers, no more chips/upgrades for you! :evil: 
July 15, 2006 11:45:37 PM

Quote:
BM, I too really like AMD's approach over the past few years. It allowed me to make some really good, reliable, cheap systems for people. I just dont see enough evidence AMD will come through with really competitive solutions early enough for my liking.

AM, can I have a link for that please, I'd like to see that out of interest. Thanks :) 


Then by all means go for Core 2. I can only tell you what I know.
July 15, 2006 11:47:56 PM

Quote:
I probably missed it, but I have yet to see a working 65nm part from AMD. You would think that after intel released 65nm production wafers almost a year ago that they would have everyone and their momma working on the shrink. Money is obviously not an issue with them since they can afford to drop billions on fabs now. They are aslso suppose to have some of the best engineering/development people in the industry. So what is the problemo?


SOI in and of itself is part of the equation --- their real problems are in my opinion.

a) Stress memorization
b) embedded SiGe
c) Dual stress memorization
d) Strained SOI

It is complicating the complicated even further --- this what I don't understand about the giddiness of all this 40% stuff earlier on and the litany of process techs. people are soooooo excited about when AMD makes press releases about this stuff.

The glossy-eyed followers who drool over such technical sounding stuff think wow --- 4 stressors.

4 Stressors just to get to within 10% of Intel's tranistor performance is a lot of engineering (and variability) to make it work. Of these stressors, 3 are new to AMD. I am not buying AMD's claims that yields are hitting milestones, if they are then their milestones are setting low standards (in my opinion).

Jack

Jack, I understand what b&d are, but what's a&c? I guess it has something to do with a certain layer cracking, but why is it an issue?


a) is a technique where special masks are applied so that when the mask is removed it maintains the shape of the gate structure.

c) is a SiGe technique that allows AMD to add more "strength" to the drains - I believe - which lowers the leakage current as you switch on and off.

I guess you could Google it like Jack would have to.

A) This is utterly incorrect.
C) Is again utterly incorrect.
B) Baron is full of BS!
July 15, 2006 11:50:25 PM

Quote:
Link.

He said Intel will transform Xeon DP product line to Woodcrest to the tune of 75 per cent by Q4.


If you average between Merom, Conroe, and Woodcrest - I have yet to see Merom numbers - it will equal 25-40% Core 2 representing all 3 families, but Centrino will cause serious price drops to move them, but improvements in perf will draw people toawrds Merom. Again if you can't sell your stock your production doesn't matter.

Intel is in a tight spot and AMD is supposedly ready to strike.
July 15, 2006 11:55:11 PM

Quote:
Intel is in a tight spot and AMD is supposedly ready to strike.

If there was discipline "Stupidity, ignorance, uneducation and boringness" in athletics, BaronBS you would be the absolute champion.
July 15, 2006 11:57:57 PM

Ha, if Intel is in such a tight spot, what is AMD in? They are implying you need no more performance than a FX currently, since more performance translates to nota in gaming, then why are they scrambling like mad to market a 4x4 (FX only) system costing many times more than their competitor, weakly attempt to equal the processing power of thy competitor? Completly stupid if performance doesn't matter... :roll:
July 16, 2006 12:01:58 AM

Quote:
BM, I too really like AMD's approach over the past few years. It allowed me to make some really good, reliable, cheap systems for people. I just dont see enough evidence AMD will come through with really competitive solutions early enough for my liking.

AM, can I have a link for that please, I'd like to see that out of interest. Thanks :) 


Then by all means go for Core 2. I can only tell you what I know.

Yes I am going for Conro, I need a new system for myself this time. I can no longer get enough out of my 4 year old system to cope with what I want. The summer is a good time for me, and Conro is by far the better choice in what will be available.

But like I said, I like AMD and found building systems around them good, and would hope I have that as a viable option in the future.
July 16, 2006 12:04:53 AM

Quote:
Everyone knows that Intel will only be 25-40% Core 2 in Q107 and that includes Woodcrest, Merom, and Conroe. AMD will be 100% AM2, S1, and 1207. They have cancelled allfo the older chips and will stop amking them soon. Thsi frees up more space for new projects and more wafers. Thsi will enale them to tweak the AM2 process even more and by Q1, AM2 will be at Rev F3. I fyou look at Rev E form E2 - E6, there were both power improvements and perf improvements. I expect the same here and that those improvements will go into Rev G 65nm.


That is awful for AMD to cancel all non-AM2 product lines! How could you admire a company for abandoning its loyal customers? Screw all socket 939 and 754 customers, no more chips/upgrades for you! :evil: 


Mayb eyou've heard about Vista, or P965. There is a finite limit to CPU upgrades. That's the way the business works. Are you saying that Core 2 should plug into Celeron boards?
July 16, 2006 12:52:12 AM

Quote:
One point to note, that even though AMD quotes a node, their Lg dimension rarely hits the ITRS roadmap --- furthermore, it is the largest on average in the MPU segment of the process. I.e. read -- not very good.



But yet still good enough to own the 4Way space.

This is irrelevant -- to the point of the discussion.

Why can you not thread crap.

Jake needs to issue a warning. This started well intended and informative. Yet we get shear ignorance crapping up the thread.

Typical of the Poser.
July 16, 2006 1:05:17 AM

Quote:
One point to note, that even though AMD quotes a node, their Lg dimension rarely hits the ITRS roadmap --- furthermore, it is the largest on average in the MPU segment of the process. I.e. read -- not very good.



But yet still good enough to own the 4Way space.

This is irrelevant -- to the point of the discussion.

Why can you not thread crap.

Jake needs to issue a warning. This started well intended and informative. Yet we get shear ignorance crapping up the thread.

First that would be SHEER. Second if he mentioned purposely that AMD has the worse specs for something it should be fair to say they still own the 4Way space.

Their 65nm schedule is on track as Jack himself posted with no mention from AMD of delays.
July 16, 2006 1:10:06 AM

STFU. Now you are using Jack as backup to your agenda? Idiot.
July 16, 2006 1:22:17 AM

Quote:
STFU. Now you are using Jack as backup to your agenda? Idiot.



Maybe he shouldn't have posted that and then questioned the process. Seems contradictory.
July 16, 2006 1:23:31 AM

Quote:
STFU. Now you are using Jack as backup to your agenda? Idiot.



Maybe he shouldn't have posted that and then questioned the process. Seems contradictory.

likewise your analytical process
!