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2mb of conroe cache disabled?

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July 16, 2006 5:48:52 AM

I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.
July 16, 2006 5:59:57 AM

Quote:
I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.


That is probably correct. That is actually the smart thing to do. This means that any part that is not fast enough to be an E6400 can be sold as an E6300. Also any part that is bad segment in the cache still has the rest of the cache that works, and therefor the bad cache can be disabled and the part can be sold as a 2M version. This is VERY smart when using cache that is so big.

Just think about it.... if Intel didn't do this, all of these parts that are sold as 6300 and below would have to be thrown out. They make more money by selling them as cheaper conroes than throwing them out.
July 16, 2006 6:06:18 AM

Okay I get it, the chips that have some of the cache malfunctioning, they disable the malfunctioning cache and other parts to make 2 of the 4 mb work, then sell it as a cheaper processor instead of throwing it away as a defective processor.
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July 16, 2006 6:27:51 AM

Quote:
Okay I get it, the chips that have some of the cache malfunctioning, they disable the malfunctioning cache and other parts to make 2 of the 4 mb work, then sell it as a cheaper processor instead of throwing it away as a defective processor.


Correct. They do the same thing with speed. They also can have a 2M version by design (as jack stated) and this saves die size, which increases yield and volume. This is all based off of binsplit and demand.

Although i dont know if this would be called "redundancy", as i think redundancy is really invincible (sp) to the end user and the same amount of cache is always available. Cache disabling you actually lose the cache.
July 16, 2006 7:00:55 AM

Quote:
I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.


This is partially correct. The 2 meg version of Conroe is called allendale -- however, during processing if defects cause issue in 2 meg's of the 4 meg L2 cache companies can simply turn off the non-function area of caches, and down brand the product and still seel it. It is called redundancy, and it helps. By doing so you can sell a normally nonfunctional die and still get a return. This is common. There is nothing wrong with the chip, it just will only access 2 of the 4 meg -- this is by design.

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

JackIt's often been said that Celerons were P4's with the defective cache disabled.
July 16, 2006 12:27:12 PM

Quote:
Okay I get it, the chips that have some of the cache malfunctioning, they disable the malfunctioning cache and other parts to make 2 of the 4mb work, then sell it as a cheaper processor instead of throwing it away as a defective processor.


Precisely --- it is better to sell down than to not sell at all :) 

A fact AMD is learning the hard way lately... but that thought hurts BM so much, it is comforting to envision the mountains of worthless P4's Intel will never be able to sell since they were never wanted anyways! :wink:
July 16, 2006 12:47:52 PM

Oh Intel isn't stupid enough to let Pentium 4s just stay there and rust. They Most probably are planning to sell them To the inter-city schools. or they might be desperate enough to give away their stock to the poorest kids in the world. Just like the computers 10X10 or 10X50 or 50X10?? we can find AMD giving away that need cranking and all that jazz., imagine poor kids in africa with crankable Prescotts. LOLLLOLS that's a lotttt of cranking kids!!
July 16, 2006 1:00:40 PM

Intel in an act of good will could donate all their older P4's to AMD, and then they could remark them Athlons! to sell as stock... all the while being able to demonstrate a smooth transition front while their design teams finish out the real McCoy on 65nm.
a c 100 à CPUs
July 16, 2006 1:06:05 PM

Yes, some lower-cache parts are in fact partially disabled or failed higher-cache parts, but more and more, they are actually separate dies. The Athlon 64 X2 Manchester (512KB) and Toledo (1MB) chips had different codenames as there were two die masks, one for each chips. It turns out that AMD had such good yields on the 1MB products that they didn't have all that many to disable the cache on to sell as 512KB models, so they simply shot 512KB dies to keep up with demand. I imagine that Intel will probably do that with the Core 2 Duo as well as Intel's yields on 65nm are supposed to be very, very good also. It also saves Intel from having to disable larger-die, perfectly functional 4MB chips to meet the demand for 2MB chips when they can use a smaller die 2MB chip from the getgo.
July 16, 2006 2:06:34 PM

Quote:
Yes, some lower-cache parts are in fact partially disabled or failed higher-cache parts, but more and more, they are actually separate dies. The Athlon 64 X2 Manchester (512KB) and Toledo (1MB) chips had different codenames as there were two die masks, one for each chips. It turns out that AMD had such good yields on the 1MB products that they didn't have all that many to disable the cache on to sell as 512KB models, so they simply shot 512KB dies to keep up with demand. I imagine that Intel will probably do that with the Core 2 Duo as well as Intel's yields on 65nm are supposed to be very, very good also. It also saves Intel from having to disable larger-die, perfectly functional 4MB chips to meet the demand for 2MB chips when they can use a smaller die 2MB chip from the getgo.
Ok, but isn't defective cache sort of "the nature of the beast"? Meaning wouldn't Intel/AMD inevitably get a certain amount of chips with defective cache?
a c 100 à CPUs
July 16, 2006 2:14:23 PM

Yes, but from what I heard, they don't get all that many defective cache chips to sell, so they need an additional smaller cache die mask and wafer run to make up the difference between demand and supply of disable-able larger-L2 chips.
July 16, 2006 2:23:44 PM

8) So would that indicate that Intel is catching up to AMD in yeilds? :wink:
a c 100 à CPUs
July 16, 2006 2:41:40 PM

Well, I think that you'd have to ask JumpingJack or JKFlipFlop98 about that one, though I bet that Intel's yields are a little better than AMD's. I use the fact that Intel never sold a cache-disabled Pentium D 9xx chip and they could sell them starting at $200 and still be in the black to back that assertion up. The most that Intel could do with a Pentium D 9xx that had bad cache would be to disable an entire core to make it a Cedar Mill P4 with a single 2M cache. I bet they would not do that if only some of the L2 cache is gone, so yields were probably good enough just to toss the few Preslers that had some cache that was defective rather than make an entirely new product line of 2x1MB 65nm Pentium Ds.
July 16, 2006 2:53:37 PM

Yep - many P4s will go overseas. People sometimes forget that there are uses for PCs outside the US.
July 16, 2006 2:56:34 PM

Quote:
Well, I think that you'd have to ask JumpingJack or JKFlipFlop98 about that one, though I bet that Intel's yields are a little better than AMD's. I use the fact that Intel never sold a cache-disabled Pentium D 9xx chip and they could sell them starting at $200 and still be in the black to back that assertion up. The most that Intel could do with a Pentium D 9xx that had bad cache would be to disable an entire core to make it a Cedar Mill P4 with a single 2M cache. I bet they would not do that if only some of the L2 cache is gone, so yields were probably good enough just to toss the few Preslers that had some cache that was defective rather than make an entirely new product line of 2x1MB 65nm Pentium Ds.


Not correct :roll: :roll: :roll: :roll: :roll:

The Pentium D's are not a true dual core, they are, essentially, two single core CPUs joined at the packaging level.

Unlike Core2 and Athlon x2 where the two cores are laid out as adjoining silicon on the original wafer, the two cores on a 8xx and 9xx dual core can and do start out as seperate single cores from different parts of the wafer (or indeed even a different wafer)

A 8xx is basically two 5xx cores on one package

A 9xx is basically two 6xx cores on one package

:p  :p  :p  :p  :p 
a c 100 à CPUs
July 16, 2006 3:17:43 PM

You are right about both Pentium D chips being MCMs (I thought that Intel had actually put the Pentium D 9xxs on one die, but apparently they did not.) However, the Pentium Ds' cores are a tad different from stock 5xx and 6xx cores:

Pentium D 8xx has two 90nm 1MB L2 cores with EM64T, EIST enabled. This most closely resembles the 5x1 series, but no 5xx chips have EIST. The 6xx ones do.

Pentium D 9xx has two 65nm 2MB L2 cores with EM64T, later steppings have EIST, the 9x0 have VT, the 9x5 ones do not. The PD 9x5 are exactly two Cedar Mill 6x1 cores whereas the PD 9x0 are two 6x2-class chips, although there are only 2 Cedar Mill 6x2 chips- the 3.8 GHz 672 (not seen in a Pentium D) and the 3.6 GHz 662, used in the PD 960. So the rest of the lower-clocked Pentium D 9x0 lineage uses 6x2 class chips not sold individually. Note that the P4 6x0 is a 2MB L2 90nm chip and is not used in a Pentium D.
July 30, 2006 4:11:02 AM

Quote:
I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.


According to this link
http://www.techpowerup.com/cpudb/details.php?id=372
The die size of Allendale is 111 mm2, while Conroe has a die size of 143.
July 30, 2006 4:13:45 AM

Quote:
I have read that the cheaper Conroe's, the E6400 and the E6300 have the exact same chip as the more expensive ones, just clocked lower and have 2mb of the 4mb of cache disabled. I bet i'm being an idiot right now but wouldnt it be logical to just keep all 4mb of the l2 cache enabled. Plus i dont see how that could be cheaper considering its the same chip.


This is partially correct. The 2 meg version of Conroe is called allendale -- however, during processing if defects cause issue in 2 meg's of the 4 meg L2 cache companies can simply turn off the non-function area of caches, and down brand the product and still sell it. It is called redundancy, and it helps. By doing so you can sell a normally nonfunctional die and still get a return. This is common. There is nothing wrong with the chip, it just will only access 2 of the 4 meg -- this is by design.

The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack

I make a motion to make you the CPU forum guru.
July 30, 2006 4:36:15 AM

Quote:
The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack
I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?
July 30, 2006 4:48:30 AM

Quote:

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?


I wonder the same thing. In fact, I bet the OEM's from TigerDirect were probably meant to clock higher, and simply are defective 6600-6800's. This would bode well for me :p . It might just mean that these have more potential than typical CPUs interms of overclocking...
July 30, 2006 4:53:26 AM

Quote:
The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack
I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.
July 30, 2006 5:10:35 AM

Quote:

I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?


I wonder the same thing. In fact, I bet the OEM's from TigerDirect were probably meant to clock higher, and simply are defective 6600-6800's. This would bode well for me :p . It might just mean that these have more potential than typical CPUs interms of overclocking...

Or it could just be wishful thinking. :lol: 
July 30, 2006 1:41:35 PM

Quote:
The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack
I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

When the extra 2 megs is disabled, one of the fuses that is blown is the Vsupply. No power will be drawn by the disabled memory.
July 30, 2006 2:29:39 PM

Quote:
The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack
I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

When the extra 2 megs is disabled, one of the fuses that is blown is the Vsupply. No power will be drawn by the disabled memory.

Ohhh yeah I thought they laser cut them but I did hear something about cache using a fuse (of sorts lol) good thinking !!!
July 30, 2006 3:28:15 PM

On the other hand, later in a products lifecycle its common to sell a WORKING core with some cache disabled etc as a lower one to fill volume orders for lower end parts when there are not enough defective ones, hence all the Radeon 9500s that got turned into 9700 Pros.

Also, there are marketing things in other areas hampering the peformance of chips, or all intel CPUs would have been on a 1066 bus for a long time now (given that almost all motherboards support it). The Pentium D 805 for example, had no reason to be on a 533mhz bus other than Intel wanting it to be differentiated from the higher chips.
a c 100 à CPUs
July 30, 2006 8:54:56 PM

Okay then JKFlipFlop, since you work at Intel, I have a question about the Allendale Core 2 Duos. Of course I know that the Conroes with some bad cache can become Allendales via blowing the Vsupply fuse, but here's what I wonder:

1. I have a suspicion that there are separate Allendale masks that can only make 2MB cache chips as yields on Conroes would be good enough that it would be wasteful to just disable the chip to meet Allendale demand. Is this true?

2. If #1 is true, then give me an estimate (if you can or are allowed to) as to what percentage of Allendales are 2M mask parts and how many are disabled Conroes.

3. If #1 is NOT true, then give me an estimate of how many Conroes that get 2MB of their L2 cache disabled really did have a bad cache and how many were just neutered to meet demand?

Thanks in advance- this is something that I was always curious about ever since there were chips with varying levels of L2 cache starting to be sold.
July 30, 2006 9:32:08 PM

Quote:
The flip side is the die size is large, so both AMD and Intel will also generate a mask set with smaller die targeted with 2 Meg L2 cache and brand those accordingly as well. In such a case, redundancy is still built in (the cache size is more like 2.5 Meg), but the die size is much smaller and you get higher yields and higher thorougput.

Jack
I have to wonder whether the binned(Conroe) parts with defective cache disabled show any difference in, say overclockability vs a specifically manufactured Allendale, or heat output...required voltage...etc. :?

Good question. I would surmise that since the extra cache is not being used (electrically), it probably would put out the same amount of heat and use the same amount of voltage.

Unless of course the disabled cache is using electricity.

When the extra 2 megs is disabled, one of the fuses that is blown is the Vsupply. No power will be drawn by the disabled memory.

Ohhh yeah I thought they laser cut them but I did hear something about cache using a fuse (of sorts lol) good thinking !!!


They did laser cut them. I remember articles going into nearly microscopic detail on how to reconnect the couple using conductive silver paint to unlock features. I didnt know they were using "fuses" now, but it makes sense . A much better way to prevent a clever kid from buying a E6300 and home brewing his own E6600. It would also save on the equipment as well a remove a physical step from the production line.

Heres an example to unlock the clock mulitplier on an old athlon 2000, but as I recall, they used the same technique on the PII/PIII lines when PIII dies failed QA. They cut em, brand em' as PII and sell em'.

http://www.tomshardware.com/2001/11/12/plastic_surgery/...


Peace
July 30, 2006 11:23:47 PM

Quote:
Okay then JKFlipFlop, since you work at Intel, I have a question about the Allendale Core 2 Duos. Of course I know that the Conroes with some bad cache can become Allendales via blowing the Vsupply fuse, but here's what I wonder:

1. I have a suspicion that there are separate Allendale masks that can only make 2MB cache chips as yields on Conroes would be good enough that it would be wasteful to just disable the chip to meet Allendale demand. Is this true?

2. If #1 is true, then give me an estimate (if you can or are allowed to) as to what percentage of Allendales are 2M mask parts and how many are disabled Conroes.

3. If #1 is NOT true, then give me an estimate of how many Conroes that get 2MB of their L2 cache disabled really did have a bad cache and how many were just neutered to meet demand?

Thanks in advance- this is something that I was always curious about ever since there were chips with varying levels of L2 cache starting to be sold.


I doubt he could tell u this as this is all yield and binsplit information which is extremely confidential at any manufacturing company. The other issue has to do with customer demand. The binsplit can be completely driver by customer demand and not actual yields. Allendale's are better to make because they have smaller die sizes and therefor you get higher yield and higher volume. But Allendale's can only be sold as 2M. For this reason, they will want to make more Conroe than Allendale, because its always good to have extra 4M versions, b/c they can always be sold as 2M. This allows Intel to have extra 4M versions if all of a sudden demand needs more 4M version that are being sold. If demand needs more 2M versions, they can just be fused as the cheaper 2M slower version. Of course, this is only if binsplit is good enough that they have extra faster parts.
a c 100 à CPUs
July 31, 2006 1:23:23 AM

Well, I guess it was worth a shot as the binsplit is exactly what I wanted to know- but I did suppose that he might not be able to say if he did know.
July 31, 2006 2:46:08 AM

Quote:
Okay then JKFlipFlop, since you work at Intel, I have a question about the Allendale Core 2 Duos. Of course I know that the Conroes with some bad cache can become Allendales via blowing the Vsupply fuse, but here's what I wonder:

1. I have a suspicion that there are separate Allendale masks that can only make 2MB cache chips as yields on Conroes would be good enough that it would be wasteful to just disable the chip to meet Allendale demand. Is this true?

2. If #1 is true, then give me an estimate (if you can or are allowed to) as to what percentage of Allendales are 2M mask parts and how many are disabled Conroes.

3. If #1 is NOT true, then give me an estimate of how many Conroes that get 2MB of their L2 cache disabled really did have a bad cache and how many were just neutered to meet demand?

Thanks in advance- this is something that I was always curious about ever since there were chips with varying levels of L2 cache starting to be sold.


1) You are correct, allendale has it's own mask set.
2) While normally we never discuss such things, I feel that I can boast a little here and tell you that less than 5% of conroe ends up in the bargain bin. the rest are allendales.
a c 100 à CPUs
July 31, 2006 2:59:25 AM

Yup, that's all I wanted to know! :D  Not trying to undertake corporate sabotage or data mining- just curious. I have read that modern CPU production results in very few defect chips- apparently this is very true and that the price considerations drive a separate mask set.

Thanks for the info, and kudos to a job well done!
July 31, 2006 10:22:17 AM

Quote:
Yup, that's all I wanted to know! :D  Not trying to undertake corporate sabotage or data mining- just curious. I have read that modern CPU production results in very few defect chips- apparently this is very true and that the price considerations drive a separate mask set.

Thanks for the info, and kudos to a job well done!


While a lot of this has to do with CPU production, a lot of this is also due to redundancy. It would take a MAJOR cache failure in order for it to not be recovered using cache recovery. Almost all cache failures can be fixed by using the extra cache banks that are included on the CPU.
July 31, 2006 3:16:52 PM

Quote:
imagine poor kids in africa with crankable Prescotts. LOLLLOLS that's a lotttt of cranking kids!!


Pitch that idea to school boards all across the U.S. Having kids in classes cranking while the others are using. It could take the place of gym class! And maybe slim down some o the fat ones.
July 31, 2006 3:26:26 PM

Quote:
imagine poor kids in africa with crankable Prescotts. LOLLLOLS that's a lotttt of cranking kids!!


Pitch that idea to school boards all across the U.S. Having kids in classes cranking while the others are using. It could take the place of gym class! And maybe slim down some o the fat ones.

You meant North America or Canada. because I'm in Canada.

Ofcourse it'll be a new way to work out It'll sure make them slim if not Armstrong. Maybe America will have lost enough wait to compete with Poor African kids in a weight off (World's skinniest Country) USA vs Sudan :twisted:
!