As such, they have a "switching time"
DRAM's latency has nothing to do with switching time: DRAM's logic switches in the order of hundreds of picoseconds, at least 5 times faster than the clock speed.
Dynamic RAMs latencies is due to the fact that they don't have "static" logic to retain data, but use capacitance, that must be refreshed every time it's read and every 64ms of no access.
In order to read the level stored in a capacitor and avoid data corruption, you must transfer at least a small amount of charge to another smaller cap, then read and regenerate throught a differential amplifier.
The charge transfer requires time, a small time, but many times longer than a static Flip Flop switching, and the bigger is the RAM in terms of capacity, the ah heck is the capacitance value.
At this time there is no standard DRAM chip that can be used in PC DIMM modules with tRC better than 50ns.
The tightest latency of tRC=20ns is only for Micron RLDRAM (Reduced Latency DRAM), used only for buffering in fast network equipment and video streaming, with maximum capacity of 588Mb (Megabit) per chip, DDR2-800 clock speed and costs 4 times a standard DRAM.
If your haste to disprove my point, you didn't complete my statement. I said
"switching time" that relates to readout and refresh. (note that I placed "switching time" in quotes.
My comments are certainly true and the point being made didn't need to delve into the switching time of an individual cell nor the specific architectural characteristics of a cell. In industry jargon, memory components are referred to as transistors. Here is a bit of an excerpt from a Micron paper speaking to the point I was making, notice the title.
Clever Architecture Instead of Faster Transistors
The speed of the DRAM memory cells themselves has increased only slightly over the years, and the column frequency (the rate at which the chip can access bit locations) of mainstream memory is unlikely to exceed 200 MHz before the end of the decade. The diagram below from Micron illustrates the challenge facing memory designers. The red line on the graph plots the relatively slow improvement in column frequency. On the yellow line are peak data rates for each of these devices, quite a dramatic contrast as memory architects come up with nonlinear improvements in the way memory cells are accessed. Since it's difficult for designers to make the memory cells much faster, higher performance must come from clever architectural improvements to the control logic surrounding the internal memory arrays.