AMD-65nm CPUs Show-up

Parrot · Jul 31, 2006

Story: HERE
:lol:

brainysmurf · Jul 31, 2006

Ha ha, gotta love those Babblefish type translations:

But control of natural enemies in residential 3600+ meat, selling points in 35W. Conroe lower than doubled consumption, low price than residential 3800+ with 4x2 3800+ while pulse, ESS CPU characteristics are many people dream.

I gather the original was in Japanese?

Parrot · Jul 31, 2006

Ha ha, gotta love those Babblefish type translations:

But control of natural enemies in residential 3600+ meat, selling points in 35W. Conroe lower than doubled consumption, low price than residential 3800+ with 4x2 3800+ while pulse, ESS CPU characteristics are many people dream.

I gather the original was in Japanese?

Chinese, actually. :lol:

RichPLS · Jul 31, 2006

Brawwk! Poly want a cracker! :lol:

BaronMatrix · Jul 31, 2006

Story: HERE
:lol:

Because the largest system desgners and builders are in Taiwan, it figures that there would Chinese coverage of the ES' known to be out there and ready for qualification. I give Oct for K8L to start showing its head. Maybe Nov.

I'm wondering if the statement about L3 is true. If so, WOW. Intel has used the L3 strategy as a "perf enhancement" so it woul dbe interesting to see what woul dhappen if they did add the L3. I would guess that they could definitely use it to help with the latency issues with DDR2. Carefully constructed L3 would make AM2/Socket F run like CAS2 DDR 400 with the extra bandwidth.

Action_Man · Jul 31, 2006

Whatever happened with reverse hyperthreading and exciting upcoming things from AMD sock puppet? :lol: 8)

xsandman · Jul 31, 2006

Story: HERE
:lol:

Because the largest system desgners and builders are in Taiwan, it figures that there would Chinese coverage of the ES' known to be out there and ready for qualification. I give Oct for K8L to start showing its head. Maybe Nov.

I'm wondering if the statement about L3 is true. If so, WOW. Intel has used the L3 strategy as a "perf enhancement" so it woul dbe interesting to see what woul dhappen if they did add the L3. I would guess that they could definitely use it to help with the latency issues with DDR2. Carefully constructed L3 would make AM2/Socket F run like CAS2 DDR 400 with the extra bandwidth.

Since when does Intel use L3 cache? Last time i checked, while Intel does have a VERY large cache, it is L2 and NOT L3. Quit spreading false information!

K8MAN · Jul 31, 2006

Story: HERE
:lol:

I think it's just assumed they at least be sampling by now since they released their roadmap stating just that to THG and Anandtech a month or 2 ago. Fab36 is currently ramping up with 65nm on 300mm wafer's and we'll see the first volume in december which should help out with AMD's current chip shortage crisis.

BaronMatrix · Jul 31, 2006

Whatever happened with reverse hyperthreading and exciting upcoming things from AMD sock puppet? :lol: 8)

I don't know. Maybe it got sick of you and decided to not come around.

BaronMatrix · Jul 31, 2006

Story: HERE
:lol:

Because the largest system desgners and builders are in Taiwan, it figures that there would Chinese coverage of the ES' known to be out there and ready for qualification. I give Oct for K8L to start showing its head. Maybe Nov.

I'm wondering if the statement about L3 is true. If so, WOW. Intel has used the L3 strategy as a "perf enhancement" so it woul dbe interesting to see what woul dhappen if they did add the L3. I would guess that they could definitely use it to help with the latency issues with DDR2. Carefully constructed L3 would make AM2/Socket F run like CAS2 DDR 400 with the extra bandwidth.

Since when does Intel use L3 cache? Last time i checked, while Intel does have a VERY large cache, it is L2 and NOT L3. Quit spreading false information!

Well, to start out recently, the Tulsa server chip has 16MB L3. pwned? naahh, just misled

Most Xeons series have had at least 1 chip with L3. Had they not used the shared cache there may have been L3 on the Conroe. One AMD chip - the K6 III - has already had L3 so it's not so far-fetched. 65 nm would let them put it on-die. DDR2 latencies have to be overcome somehow.

This would cost a little die but it would help with latency. Even 1MB would hide a lot of latency. Once latencies catch up this would improve perf even more.

RichPLS · Jul 31, 2006

dreaming only gets you so far, time for action, man.

kukito · Jul 31, 2006

Story: HERE
:lol:

Finally!

Action_Man · Jul 31, 2006

Whatever happened with reverse hyperthreading and exciting upcoming things from AMD sock puppet? :lol: 8)

I don't know. Maybe it got sick of you and decided to not come around.

I think he got sick of you giving AMD fans a bad name. :roll:

xsandman · Jul 31, 2006

Well, to start out recently, the Tulsa server chip has 16MB L3. pwned? naahh, just misled

Most Xeons series have had at least 1 chip with L3. Had they not used the shared cache there may have been L3 on the Conroe. One AMD chip - the K6 III - has already had L3 so it's not so far-fetched. 65 nm would let them put it on-die. DDR2 latencies have to be overcome somehow.

This would cost a little die but it would help with latency. Even 1MB would hide a lot of latency. Once latencies catch up this would improve perf even more.

Correct, Tulsa uses L3 cache. Tulsa has not been released yet. Tulsa also has 16MB of L3 cache and this is for EXTREMELY high end MP servers.

All CURRENT Xeon and Desktop processors do NOT have ANY L3 cache as you make it sound. And Tulsa will be the ONLY chip (again for VERY expensive MP systems) that has an L3 cache.

Therefor Intel is NOT using an L3 strategy on ANY of the current products, and will NOT be using this strategy on ANY mainstream products ANYTIME soon.

BaronMatrix · Jul 31, 2006

Correct, Tulsa uses L3 cache. Tulsa has not been released yet. Tulsa also has 16MB of L3 cache and this is for EXTREMELY high end MP servers.

All CURRENT Xeon and Desktop processors do NOT have ANY L3 cache as you make it sound. And Tulsa will be the ONLY chip (again for VERY expensive MP systems) that has an L3 cache.

Therefor Intel is NOT using an L3 strategy on ANY of the current products, and will NOT be using this strategy on ANY mainstream products ANYTIME soon.

Just give up Xeon lines have always had at least one chip with L3. Google Xeon L3.

xsandman · Jul 31, 2006

Correct, Tulsa uses L3 cache. Tulsa has not been released yet. Tulsa also has 16MB of L3 cache and this is for EXTREMELY high end MP servers.

All CURRENT Xeon and Desktop processors do NOT have ANY L3 cache as you make it sound. And Tulsa will be the ONLY chip (again for VERY expensive MP systems) that has an L3 cache.

Therefor Intel is NOT using an L3 strategy on ANY of the current products, and will NOT be using this strategy on ANY mainstream products ANYTIME soon.

Just give up Xeon lines have always had at least one chip with L3. Google Xeon L3.

This is STILL not a mainstream high volume product! Your argument that "Intel has used the L3 strategy as a "perf enhancement"" has no basis in the mainstream market. This is for exlusive processors only. Your point is moot.

BaronMatrix · Jul 31, 2006

Correct, Tulsa uses L3 cache. Tulsa has not been released yet. Tulsa also has 16MB of L3 cache and this is for EXTREMELY high end MP servers.

All CURRENT Xeon and Desktop processors do NOT have ANY L3 cache as you make it sound. And Tulsa will be the ONLY chip (again for VERY expensive MP systems) that has an L3 cache.

Therefor Intel is NOT using an L3 strategy on ANY of the current products, and will NOT be using this strategy on ANY mainstream products ANYTIME soon.

Just give up Xeon lines have always had at least one chip with L3. Google Xeon L3.

This is STILL not a mainstream high volume product! Your argument that "Intel has used the L3 strategy as a "perf enhancement"" has no basis in the mainstream market. This is for exlusive processors only. Your point is moot.

Dude you're like that dumb kid who doesn't give up. My point was that the link mentioned L3 I said it would help perf and Intel and AMD have used it. I didn't say anything about the market they were introduced in.

Get a life.

Mind_Rebuilding · Jul 31, 2006

Story: HERE
:lol:

Just a photo of a phototype processor.

chuckshissle · Jul 31, 2006

Whatever happened with reverse hyperthreading and exciting upcoming things from AMD sock puppet? :lol: 8)

Not anymore, AMD is still feeling like a kitten kicked to the wall.

chuckshissle · Jul 31, 2006

Nice shirt dude.

Mind_Rebuilding · Jul 31, 2006

Story: HERE
:lol:

Pretty packaging.... when it boots windows then get back to us.

Jack

I agree.

I can read Chinese.
The poster just tried to describe a prototype processor without any booting.

jkflipflop98 · Jul 31, 2006

According to that CAD render, AMD has put thier L3 cache all the way against the far left side of the die. Kinda dumb if it's supposed to be shared across both logic units.

chocobocorey · Jul 31, 2006

i think there was an extreme edition of the p4 befroe with l3 cache... maybe..

BaronMatrix · Jul 31, 2006

Story: HERE
:lol:

Pretty packaging.... when it boots windows then get back to us.

Jack

It says ES. What do you want? Aren't you the one who posted the EDT, EVT schedule? They should be showing up in pics. Like I said I would expect to see K8L in ~Oct.

BaronMatrix · Jul 31, 2006

Whatever happened with reverse hyperthreading and exciting upcoming things from AMD sock puppet? :lol: 8)

Not anymore, AMD is still feeling like a kitten kicked to the wall.

So what you're saying is that I should down Intel like you down AMD because I happen to buy AMD?

OK!

Fortunately I won't hold Intel fully responsible for you.

AMD-65nm CPUs Show-up

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