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The Inquirer: Intel quad-cores likely to use 1333FSB

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August 1, 2006 12:06:09 PM

I'm pretty bored so enjoy!

Link.

More about : inquirer intel quad cores 1333fsb

August 1, 2006 12:13:12 PM

I love the inquirer. Best site ever anyways damn WoW servers are down for maintenance, damn crappy blizzard.

Anyways, it'd certainly be interesting to see what sort of difference it'd make.
August 1, 2006 12:17:08 PM

Why? Theres a decent speed up with a 1333fsb on conroe, I'm sure the extra bandwidth would help.
Related resources
August 1, 2006 12:52:56 PM

Pretty narrow bandwidth to feed 4 cores :roll: Can have a bad impact on performance.
August 1, 2006 1:03:20 PM

Most probably... Accepting a minimum of 400MHz BW / Core of an EARLY P4, Core2 CPUs process much more data/clock, even more than K8s so a Quad Core2 sould have at least a 1600MHz channel to transfer the larger amount of data it processes.
Furthermore, a 1333FSB falls short in using all the Dual DDR2 800.
August 1, 2006 1:08:00 PM

Merom only uses a 667 fsb and it clocks up to 2.33ghz.
August 1, 2006 1:10:57 PM

Looks like commonsense to me but I would say as much as 2000mhz if their new core is so efficient,,,but SOBs at intel will sell this "1333" as the best ting since slced bread & many will think so.
They need to swallow their pride & go with a IMC.
August 1, 2006 1:13:17 PM

You need to look up what CSI is (and no not the show)
August 1, 2006 1:14:17 PM

For desktops that might not be much of a problem but for servers with multicore cpus & sacling, it will be a problem i think,,,AM SURE.
August 1, 2006 1:24:38 PM

Quote:
Merom only uses a 667 fsb and it clocks up to 2.33ghz.

Does not mean that's enough. It's a laptop CPU and we're talking about desktop/server.
August 1, 2006 1:29:44 PM

It'll be enough, theres only a ~2.5% increase for conroe going for 1066 to 1333.
August 1, 2006 1:35:31 PM

If thats all its not worth it,,, it sucks.
There has to be more.
Enlighten us.
August 1, 2006 1:36:08 PM

Conroe is only dual Core: 1066/2 = 533 MHz/Core AT LEAST (667MHz/core for the 1333 version)
While for 4 cores you have 1333/4 = 333 MHz/Core, that's AthlonXP levels, half that of Conroe, it will definitely be pretty crippling.
August 1, 2006 4:51:29 PM

Quote:
Conroe is only dual Core: 1066/2 = 533 MHz/Core AT LEAST (667MHz/core for the 1333 version)
While for 4 cores you have 1333/4 = 333 MHz/Core, that's AthlonXP levels, half that of Conroe, it will definitely be pretty crippling.


Sounds like what they told about the Conroe too.

*OMG! Conroe still uses FSB! One FSB to feed 2 cores! TWO Cores! OMG!
*OMG! Conroe doesn't have an IMC! A processor in 2006 without an IMC! OMG!
*OMG! Conroe is made by Intel! By Intel! That stupid company still makes CPUs!
August 1, 2006 5:26:17 PM

Well they should. Woodcrest uses a 1333 right. And thats only a dual core.


PS: Whats with the cat?
August 1, 2006 6:00:11 PM

I think they should have gone for the 1337 front side bus. It's just so much better from a marketing standpoint. :D 


Sorry for going off topic here, but whats with the cat icon?
August 1, 2006 6:03:59 PM

Quote:
I think they should have gone for the 1337 front side bus. It's just so much better from a marketing standpoint. :D 


Sorry for going off topic here, but whats with the cat icon?


:lol:  :lol:  :lol:  1337mhz FSB would do intel well :p 
a c 480 à CPUs
a c 119 å Intel
August 1, 2006 7:37:13 PM

Quote:
I'm pretty bored so enjoy!

Link.


Sorry, but I won't believe until I read about it somewhere else.
August 1, 2006 9:14:44 PM

Quote:
Well they should. Woodcrest uses a 1333 right. And thats only a dual core.


PS: Whats with the cat?


"And that's only dual core" is a key point. Intel's quad cores are going to be (initially) two dies stuck together under a single IHS. This means there are two loads on the FSB, which makes higher FSB harder to achieve.
August 1, 2006 9:40:18 PM

Quote:
Conroe is only dual Core: 1066/2 = 533 MHz/Core AT LEAST (667MHz/core for the 1333 version)
While for 4 cores you have 1333/4 = 333 MHz/Core, that's AthlonXP levels, half that of Conroe, it will definitely be pretty crippling.


Sounds like what they told about the Conroe too.

*OMG! Conroe still uses FSB! One FSB to feed 2 cores! TWO Cores! OMG!
*OMG! Conroe doesn't have an IMC! A processor in 2006 without an IMC! OMG!
*OMG! Conroe is made by Intel! By Intel! That stupid company still makes CPUs!

Personally I never thought FSB 1066 would be a problem for Conroe and of course it won't keep 4 cores from outperforming 2 of them but performance will not be fully unleashed if they use that FSB; nothing personal with Intel but they're just numbers; one of those cores will work with 333MHz FSB, one of Conroe's works with 667MHz.
However, I think sooner or later, Intel will "invent" some new technology, name it something like "upper traffic technology" and go ahead with it :D 
August 1, 2006 9:48:18 PM

If dual core P4's can survive on an 800fsb I'm sure quad conroe will be fine with 1333. Anyways coolaler or whatever his name is has a quad core and it was fine with only a 1066 fsb.
August 1, 2006 9:53:25 PM

Quote:
If dual core P4's can survive on an 800fsb I'm sure quad conroe will be fine with 1333. Anyways coolaler or whatever his name is has a quad core and it was fine with only a 1066 fsb.


coolaler doesnt have kentsfield anymore... he sold it on yahoo auctions (ebay for taiwan) for 40k NT, thats around 1337USD =/ starting bid was 30 bucks USD... he ran fine w/ kentsfield at 1066fsb, no lag or anything, not like all the cores are used at once and stole bandwith ;)  but i doubt the FSB will be a problem anytime soon
August 1, 2006 9:55:58 PM

He did run 4 instances of super pi at once.

Quote:
thats around 1337USD


Hehe leet dollars.
August 1, 2006 9:57:43 PM

Quote:
He did run 4 instances of super pi at once.

thats around 1337USD


Hehe leet dollars.

and it wasnt made 1337 dollars on purpose :p 
August 1, 2006 10:02:00 PM

:lol:  :lol:  :lol:  what if intels bus speed was 334.4 mhz? (1337.2 when quad pumped)
August 1, 2006 10:14:15 PM

Quote:
If dual core P4's can survive on an 800fsb I'm sure quad conroe will be fine with 1333. Anyways coolaler or whatever his name is has a quad core and it was fine with only a 1066 fsb.


They survived sure but scaled very poorily. 1066 to 1333 is only a tiny increase in IO bandwidth on a shared bus but the number of cores will double. It seems especially poor since the quad core is effectively two dual cores glued together requiring off chip communication as well. The Conroes memory prefectchers are very good so maybe that will help but i dont think it will be as good as the scaling on the K8 native quad core.
August 1, 2006 10:28:04 PM

Quote:
If dual core P4's can survive on an 800fsb I'm sure quad conroe will be fine with 1333. Anyways coolaler or whatever his name is has a quad core and it was fine with only a 1066 fsb.


Nobody put in discussion survival. However, it looks like intel is approaching another dead-end: FSB. They have the raw power to do everything they want but don't think much ahead; AMDs quad cores are not to be released much later than Intel's and if they get the right architecture to compete with Core2, they will have HyperTransport2 on their side.
August 1, 2006 10:38:36 PM

Quote:
If dual core P4's can survive on an 800fsb I'm sure quad conroe will be fine with 1333. Anyways coolaler or whatever his name is has a quad core and it was fine with only a 1066 fsb.


Nobody put in discussion survival. However, it looks like intel is approaching another dead-end: FSB. They have the raw power to do everything they want but don't think much ahead; AMDs quad cores are not to be released much later than Intel's and if they get the right architecture to compete with Core2, they will have HyperTransport2 on their side.

intel would get a new tech, but for now FSB is enough bandwith
August 1, 2006 10:43:57 PM

AMD's quad cores are just straight die shrinks.
August 1, 2006 10:45:04 PM

:lol:  I have that on my ipod.
August 1, 2006 10:48:14 PM

Um ya, whatever, that news is pretty insignificant when you compare it to the death of T-rex. Whats up with the kitty?

Peace
August 1, 2006 10:48:37 PM

Quote:
Nobody put in discussion survival. However, it looks like intel is approaching another dead-end: FSB. They have the raw power to do everything they want but don't think much ahead; AMDs quad cores are not to be released much later than Intel's and if they get the right architecture to compete with Core2, they will have HyperTransport2 on their side.


Intel already realizes the need for an IMC:

http://www.xbitlabs.com/news/cpu/display/20060615075534.html

Quote:
Intel admitted that built-in memory controller helps to reduce memory access latencies and eliminate memory controller hub as an additional component. But the world’s largest maker of microprocessors defended its current stance saying that by incorporating larger caches – on-chip memory pools – it can reduce memory latency impacts. At the same time, building memory controller into processor results in increased die size and power consumption of the CPU and reduces flexibility between supported memory types.

Nevertheless, according to eWeek web-site, Mr. Bhandarkar indicated that his company “probably” would “put the memory controller on the chip at some point”



I'm sure it will make its way onto their next platform. Which, according to Intel, will be in 2 years. I doubt the fsb will be a problem with current generation. With all the hype Intel has right now, I doubt they would introduce this design if it was bottlenecked at this speed.
August 1, 2006 10:50:15 PM

Quote:
Nobody put in discussion survival. However, it looks like intel is approaching another dead-end: FSB. They have the raw power to do everything they want but don't think much ahead; AMDs quad cores are not to be released much later than Intel's and if they get the right architecture to compete with Core2, they will have HyperTransport2 on their side.


Intel already realizes the need for an IMC:

http://www.xbitlabs.com/news/cpu/display/20060615075534.html

Quote:
Intel admitted that built-in memory controller helps to reduce memory access latencies and eliminate memory controller hub as an additional component. But the world’s largest maker of microprocessors defended its current stance saying that by incorporating larger caches – on-chip memory pools – it can reduce memory latency impacts. At the same time, building memory controller into processor results in increased die size and power consumption of the CPU and reduces flexibility between supported memory types.

Nevertheless, according to eWeek web-site, Mr. Bhandarkar indicated that his company “probably” would “put the memory controller on the chip at some point”



I'm sure it will make its way onto their next platform. Which, according to Intel, will be in 2 years. I doubt the fsb will be a problem with current generation. With all the hype Intel has right now, I doubt they would introduce this design if it was bottlenecked at this speed.

:? heh intel IMC is gonna totally kick ass :p 
August 1, 2006 11:28:48 PM

Any movement in the direction of a 1333MHz FSB is good. Really it isn't that hard. The highest Kentsfield I've found was by sierra_bound at 1508MHz and a clock speed of 3769MHz. This was by aircooling too.

http://www.xtremesystems.org/forums/showthread.php?t=10...

For interest coolaler reached a 1484MHz FSB for a 3710MHz clock speed. He was using a i975X chipset and was running 2 7900GTX in SLI mode.

http://www.xtremesystems.org/forums/showthread.php?t=10...

I think the best thing that Intel could do is release the Extreme Edition as a 2.67GHz 1333MHz FSB Kentsfield for $999 with a 120W TDP. Then they could release a 2.13GHz 1066MHz FSB Kentsfield for $637 (Pentium 4 571 price point) with a 80W TDP. This way they could get a decent performing Extreme Edition part while also having a 1066MHz part so that 965 series chipset users aren't left out. The lower price point 1066MHz Kentsfield will also be important if the 4x4 platform really is aggressively priced.

Then in Q2 2007 when the Bearlake platform is released Intel can refresh with a 3GHz 1333MHz Extreme Edition (120W TDP) and a 2.4GHz 1066MHz mainstream part (80W TDP). The reason why I suggesteded the 120W TDP for the Extreme Edition was to account for the 3GHz model since I don't think Intel can make it on the current projected 110W TDP. The 80W TDP for the 2.4GHz part is a bit of a stretch, but since the 2.33GHz 1333MHz FSB LV Woodcrest has a 40W TDP it is possible. Especially as the process improves by Q2. The 2.13GHz part can drop in price and a 2.67GHz 1066MHz FSB mainstream part with the higher 120W TDP is also possible. These should hold Intel out until Q4 2007 when the 45nm single die quad cores can arrive. Hopefully those quad cores will up the FSB again to 1600MHz for the Extreme Edition which is perfectly possible for a single die solution. A 1600MHz FSB should also be perfectly adequate for a single die quad core given that there would no longer be cache coherency and 45nm would allow larger shared caches.
August 1, 2006 11:51:40 PM

The kentsfield is fine with a 1066 mhz fsb, it being at 1333 mhz will only be better, and most likely eliminate any fsb bottleneck that amd fans may claim. But I think its fast enough with the 1066 mhz fsb... look at this and see for your self. Amd quad cores are going to get completly slaughtered....

http://www.xtremesystems.org/forums/showthread.php?t=10...
August 2, 2006 1:47:07 AM

Quote:
The kentsfield is fine with a 1066 mhz fsb, it being at 1333 mhz will only be better, and most likely eliminate any fsb bottleneck that amd fans may claim. But I think its fast enough with the 1066 mhz fsb... look at this and see for your self. Amd quad cores are going to get completly slaughtered....

http://www.xtremesystems.org/forums/showthread.php?t=10...


Intel's FSB is ancient, dating back to god knows when, its the weakest part of their architecture. It was never designed for anything other than single core desktop machines. It has survived for so long because Intel was able to keep ramping up the frequency but that will hit a wall soon (P4 anyone?) and also it does nothing to help mitigate the inefficiencies and very poor scaling of a shared bus. The older P4 Xeons were terrible performers in 2P and above configurations because of the llimitations of their shared FSB. For desktops 1333Mhz is adequate but as soon as we go to the server market its just well sh*t in multiprocessor configurations. Intel should have taken a second bitter pill when they where forced by Microsoft to use AMD 64 extension and also licensed HyperTransport or got a move on with bringing CSI to the market.
August 2, 2006 1:55:05 AM

heh heh... considering how ancient and shoddy a design Intel uses, must be even more of a devestation that such low tech & glued (elmers at that) together crap can kick AMD's streamlined SoI chip with sophesticated IMC and all that bandwidth.
August 2, 2006 2:03:20 AM

Quote:
heh heh... considering how ancient and shoddy a design Intel uses, must be even more of a devestation that such low tech & glued (elmers at that) together crap can kick AMD's streamlined SoI chip with sophesticated IMC and all that bandwidth.


"It's the chip that made the Kessel run in less than twelve parsecs!" 8O
August 2, 2006 2:11:35 AM

Quote:
heh heh... considering how ancient and shoddy a design Intel uses, must be even more of a devestation that such low tech & glued (elmers at that) together crap can kick AMD's streamlined SoI chip with sophesticated IMC and all that bandwidth.


Indeed. Dont get me wrong, I didn't say anything is wrong with the C2D but the plaform it sits on. Get Intel to put some of that IMC and bandwidth onto the C2D and AMD will be well and truely dog meat.
August 2, 2006 2:17:36 AM

Quote:
heh heh... considering how ancient and shoddy a design Intel uses, must be even more of a devestation that such low tech & glued (elmers at that) together crap can kick AMD's streamlined SoI chip with sophesticated IMC and all that bandwidth.


Defensive arent we. I didn't say anything about the C2D mearly the shiteness of the shared FSB. Get Intel to put some of that IMC and bandwidth onto the C2D and AMD will be well and truely dog meat.



Not necessarily. Jack gave me a very thorough explanation of the Core 2’s off die mc vs. AMD's imc. Sound’s like Intel’s approach (at least with core 2) was equitable with AMD's imc

Ask Jack about it.

Peace
August 2, 2006 2:27:43 AM

Quote:
heh heh... considering how ancient and shoddy a design Intel uses, must be even more of a devestation that such low tech & glued (elmers at that) together crap can kick AMD's streamlined SoI chip with sophesticated IMC and all that bandwidth.


Defensive arent we. I didn't say anything about the C2D mearly the shiteness of the shared FSB. Get Intel to put some of that IMC and bandwidth onto the C2D and AMD will be well and truely dog meat.



Not necessarily. Jack gave me a very thorough explanation of the Core 2’s off die mc vs. AMD's imc. Sound’s like Intel’s approach (at least with core 2) was equitable with AMD's imc

Ask Jack about it.

Peace

I will. C2D does not have its own off die specific MC. I was under the impression that the C2D memory prefetchers did a lot of clever stuff on chip to get around the problems of shared FSB and off chip MC. Thats why it has latencies on par with AMDs and works well with slower memory. Trouble is with 2P+ scaling is still rather bad. Xeon 5XXX series has 2 FSB requiring two MCs i think but that aint gonna scale well beyond 2P at all.

edit: typos
edit2: more typos
August 2, 2006 2:27:43 AM

The good thing about off die IMC is that it can use any memory for the desired system, so ppl that have DDR and wants a conroe wont be in deep shit
August 2, 2006 2:37:23 AM

Well,
I am not nearly well versed enough in the subject to debate intelligently.

Quote:
Trouble is with 2P+ scaling is still rather bad. Xeon 5XXX series has 2 FSB requiring too MCs i think but that aint gonna scale well beyond 2P at all.



Jack is one of the experts in residence. He knows more about Uarch than I ever can hope to. I would be very interested to see his response on this subject. Hopefully he will indulge us.

Peace
August 2, 2006 3:37:14 AM

Thanks Jack

Another question if I may, its probably stupid, but...

Lots of talk going on about Intel bottlnecking the FSB on the 4cores. Is it a moot point considering data flow through other weak spots, i.e. the PCIe buss, HDDs etc?

Peace
August 2, 2006 3:56:16 AM

Quote:
Trouble is with 2P+ scaling is still rather bad. Xeon 5XXX series has 2 FSB requiring two MCs i think but that aint gonna scale well beyond 2P at all.

The Bensley platform provides support for 2 1333MHz FSBs and 1 quad channel FB-DIMM MC. Theoretically, 2 Woodcrests should have no memory bandwidth problems. A standard dual core ship doesn't really need the whole 1333MHz FSB, which is why Conroe does just fine on a 1066MHz FSB. However, the extra bandwidth is useful for cache-coherency traffic.

In terms of Cloverton, a 1067MHz FSB is a a noticeable limitation. In Woodcrest, 2 caches had to be kept coherent across 2 1333MHz FSBs, so that isn't a problem. However, with Cloverton 4 caches need to use 2 1067MHz FSBs. This is where 1333MHz FSBs are really needed. Still, the shared caches are beneficial since the number of caches to be kept coherent are cut in half. Personally, I like to quote 533MHz per cache (for a 1067MHz FSB) rather than 267MHz per core due to the shared cache.

Now in terms of 4P Xeon MP systems, they will transition to Core 2 in Q3 2007 with Tigerton. It will appears to still be a 2 die solution. Previously there was a Cloverton MP, which may be Tigerton. However, it's also possible that Tigerton will be a 2x8MB L2 cache processor. The additional cache will help alleviate the FSB bottleneck.

However, the major change is the Truland platform Tigerton will launch on. Truland will provide 4x1067MHz FSBs with a 6 channel 667MHz FB-DIMM memory controller. If Tigerton really has 2x8MB cache, then this setup should be sufficient. Personally, I was hopeing that Tigerton would have a shared L3 cache like Tulsa does, that way there would only be 4 caches to be kept coherent instead of 8. However, it seems that a shared L3 cache will have to wait until Dunnington, a single die quad core 45nm solution in 2008.

Still, I think that the Truland platform is adequate, but could be made better. First, 4x1333MHz FSB support is critical. The thing holding that back is the processor, but if Kentsfield and Cloverton support 1333MHz FSBs, then no doubt Tigerton can too. Besides, Tigerton won't arrive for another year and has a platform designed in parallel so you'd think Intel would have plenty of time to work out whatever problems there are to getting 1333MHz FSBs stable by then. Preferrably, the 4x1333MHz FSBs would be supported by an 8 channel 667MHz FB-DIMM memory controller for a clean setup. However, an 8 channel memory controller isn't likely, although there were rumours that future Itaniums would integrate it. The next best thing would be for the 4x1333MHz system to be supported by a 6 channel 800MHz FB-DIMM system. It could also use DDR3 800 FB-DIMMs which will help reduce power consumption and should be available by Q3 2007. If availability is low or prices are high, DDR2 800 FB-DIMMs could also be used on the same motherboard since the specific type of memory is irrelevent when using the FB-DIMM interface.

In any case, you are right that previously Xeons had poor scaling because 2P setups used 1 FSB, and 4P setups used 2 FSBs. Now, that will double. 4 processors on 4 FSBs may not be the most elegent solution, but it'll do. FSBs really aren't that much of a limiting factor right now. What Intel needs to do right now though, is figure out how to optimize the memory controllers. Conroe isn't using it's full theoretical FSB bandwidth, and FB-DIMMs have particularly poor scaling considering it's 4 channels in Bensley. They should worry about filling up their current FSBs before getting bigger ones.
August 2, 2006 4:33:09 AM

Thanks Jack

Peace
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