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How important is the timing in RAM

Last response: in Memory
August 23, 2006 3:10:46 PM

Hi Guyz

Can some please explain to me how it works with the timing in RAM?

Whats a good timing?
Why do I need a good timing?
Is it going to help with overclocking?
is it worth spending the extra couple of dollar for better timing?

for example let say you got
G.SKILL 2GB(1GB x 2) PC2-6400 (DDR2-800) 4-4-4-12 Dual
G.SKILL 2GB Kit (2x1024MB) F2-6400PHU2-2GBNR 5-5-5-15
G.Skill 2GBHZ-D1H 2GB (2x1024MB) PC4000 3-4-4-8 w/heatspreader

which one is the best, second and last?

thanks in advance for replies

More about : important timing ram

August 23, 2006 3:31:00 PM

The Lower timings the better, if ur using core duo 2, its pritty forgiving with ram timing.
August 23, 2006 3:57:16 PM

The timing ratings refer to the number of cycles it takes to do some operations. Therfore the speed of the RAM is also important. There is no point in having RAM that goes 33% faster if the timing ends-up being twice as long. I think the ranking, from best to worst would therefore be:
    [*:22e12a6a07](DDR2-800) 4-4-4-12[*:22e12a6a07]F2-6400PHU2-2GBNR 5-5-5-15[*:22e12a6a07]PC4000 3-4-4-8The last 2 I'm not sure since I have no idea what each timing rating implies. If I made any mistake, please someone tell me, I like to improve my knowledge just like anyone else.
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August 23, 2006 4:15:54 PM

Whats a good timing?

It depends on the clock frequency: the timing is expressed in clock periods (not the DDR clock, but the real clock that is exaclty the half).
The formula is: Tns = T * (1000 / Fclk)
Tns = the timing in nanoseconds
T = the timing number stated in the RAM specs
Fclk = the clock frequency (as I said, half the DDR speed)
For example the 3 RAMs you mentioned have this CL (CAS Latency, the first number and more important timing) in order:
4 * (1000 / 400) = 10ns
5 * (1000 / 400) = 12.5ns
3 * (1000 / 250) = 12ns

A very good memory has a CL of 10ns that is CL2 for DDR-400 and CL4 for DDR2-800.

Why do I need a good timing?

Because dynamic RAMs access data in very small consecutive burst: every time you need to access non consecutive data or you have to start a new burst there is a fixed time needed for the RAM to accomodate for the new data transfer. This is called latency and is the time the CPU must wait on average for every memory access.
The lower the latency, the higher the performance.

Is it going to help with overclocking?

Yes it can, because when you raise the clock speed you need to slow the timings, so it's important to have a memory with very tight timing on stock setup, so it won't loose performance when you raise them for OCing.

is it worth spending the extra couple of dollar for better timing?

If you plan to OC or using very memory intensive applications (image processing, 3D modeling, simulations) yes.
But for gaming it's usually better invest in a faster and bigger RAM than a smaller with tight timings.

which one is the best, second and last?

The last is not DDR2, it's uncomparable because you can't use it with the same mobo processors as the others.
Anyway the best is the first: as you can see it has the highest frequency and the lowest timings, wich is always better.
August 23, 2006 4:43:37 PM

RAM timing are very important i have my ram at 3-3-3-2 and 2,8V and is't blazing fast that the default ones
August 23, 2006 4:45:38 PM

I have no idea what each timing rating implies

I'll give you a small reference, if you want to go further search for DRAM in Wiki.

The timings are specified like this: A-B-C-D
A = tCL (CAS Latency)
B = tRCD (RAS to CAS Delay)
C = tRP (Row Precharge)
D = tRAS (Row Active)

DRAMs are organized in row and column and RAS# (Row Address Strobe) and CAS# (Column Address Strobe) are two signals needed to tell the RAM with are sending the row or column address because they are sent on the same wires in different moments in order to simplify the internal logic and reduce the number of wires.

tCL is the delay between the CAS# signal and the data output from the RAM: it's the delay the RAM sends out data after you provided the column address and since column addresses change on average 10 times over a single row change it's the most important timing and directly affects the system performance in random access.

tRCD is the time you need to wait between the RAS# and CAS# signals: you must wait at least the tRCD time before selecting a column after you opened a row. It's not much important in fast clocked RAMs, since row addresses change on average every 10 column address change.

tRP is the time needed to close row: rows are organized in 4 banks and when you change the row address you must wait at least tRP before opening another row in the same bank. This is not very important because the memory controllers usually access the banks in sequence, so while the chip is closing a row in a bank the controller reads data on another bank, allowing the precharge process to be in background.

tRAS is the minimum time required to open a row, a column in it, read data and close the row. It's the least important (timings are listeed in importance order for performace) and it directly depends on the others.

I hope this very small reference is might be useful.