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Is AMD ashamed of showing 65nm ES?!

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August 28, 2006 5:17:23 PM

Quote:
hit our tender ears about what AMD's problems at 65nm are rather than the nebulous 'they have issues'. A bird has been singing to us that AMD is having problems getting the speeds they need out of the stock voltages.
This is forcing AMD to pump things as high as 1.4V. If you do the math, (1.4^2)/(1.1^2) = 1.62, so AMD is forced to use 60+% more power than they wanted to. This kind of skews the performance per watt leadership they are claiming, so I guess there is still work to be done.

That said, there is a bit more than three months to go before any deadlines are missed, and the wafers going in today are still not the ones you may end up buying, so there is time. Barely. µ


http://www.theinquirer.net/default.aspx?article=33964

Can somebody - above 12 - elaborate how going 65nm increases power consumption? Or this is just another BS from Edited?!

,,
August 28, 2006 5:51:49 PM

Hi,
Shrinking to 65 nm can increase transistor leakage current. If i remember correctly , intel had this problem as well.
August 28, 2006 5:53:39 PM

Quote:
hit our tender ears about what AMD's problems at 65nm are rather than the nebulous 'they have issues'. A bird has been singing to us that AMD is having problems getting the speeds they need out of the stock voltages.
This is forcing AMD to pump things as high as 1.4V. If you do the math, (1.4^2)/(1.1^2) = 1.62, so AMD is forced to use 60+% more power than they wanted to. This kind of skews the performance per watt leadership they are claiming, so I guess there is still work to be done.

That said, there is a bit more than three months to go before any deadlines are missed, and the wafers going in today are still not the ones you may end up buying, so there is time. Barely. µ


http://www.theinquirer.net/default.aspx?article=33964

Can somebody - above 12 - elaborate how going 65nm increases power consumption? Or this is just another BS from edited?!

,,

*edit* Removed ambiguous statement */edit*

I'm sure AMD will have their sh!t together by the time they release, whether or not they miss their deadline. This kind of report is like saying, "Hey, Windows Vista has a bug in it before it's released!". "No sh!t. Who cares?"

Thanks to the INQ for wasting more internet bandwidth.
Related resources
August 28, 2006 10:26:50 PM

Quote:


I'm sure AMD will have their sh!t together by the time they release, whether or not they miss their deadline. This kind of report is like saying, "Hey, Windows Vista has a bug in it before it's released!". "No sh!t. Who cares?"

Thanks to the INQ for wasting more internet bandwidth.



Lol, yeah, but by the time widows vista is released, with all the features they've been cutting, its going to be little more than the transition from Win98 to WinME was. A little window dressing (eye candy), more resouces consumed and a performance decrease.
August 28, 2006 11:28:50 PM

I would assume the problem is something along the lines of electron migration on the transistors, since they are closer together.
August 29, 2006 5:37:17 AM

Quote:
Follow up --- overclockers.com Mr. Ed did a serious injustice to AMD

He claimed:

What's the likely problem? Given that these chips are basically just process shrinks of current 90nm chips, the problem most probably is the SOI process.

http://www.overclockers.com/tips01023/

Before this thread locks up (if it does), I want to ensure I chastise the author some on this Ed-itorial. :) 


AMD's 65 nm process is much more than simply a shrink of the 90 nm process, sure maybe masks are a shrink but the process itself contains 3 new stressing techniques, a shallower surface Si overlayer, and due to embedded SiGe a new silicide for contact formation (likely NiSi).

This is anything but a straight up shrink, furthermore, it has not even been established that there is a problem ....... shame on Ed.

THis is one more example with instigating rumors such as this without good proof, a brief statement of mole digging run amuck --- the Inquirer should be shut down completely.

Jack

Ok before this thread gets locked down and burns in hell I would like to thank you Jack for your insights, this was new news to me but apparently old news to forumz. Ok lets' call friends and mods and Anand to lock it down and remove this national security threat (previously thread) which is not less hazardous than a 60 years old lady on a plane carrying a pencil.

,,
August 29, 2006 8:52:54 AM

Isn’t the whole idea that AMD’s 65nm desktop chips were ever intended to run at 1.1V questionable in the first place?
That seems too low when you look at current voltages for Intel at 65/90nm and AMD at 90nm. Conroe is rated up to 1.325V and AM2 X2s are typically up to 1.35V.
The only major exception is the 35W X2 3800 rated at 1.025/1.075V. But those are specialised low volume parts so hardly indicative of anything.
August 29, 2006 12:46:40 PM

Quote:
Isn’t the whole idea that AMD’s 65nm desktop chips were ever intended to run at 1.1V questionable in the first place?
That seems too low when you look at current voltages for Intel at 65/90nm and AMD at 90nm. Conroe is rated up to 1.325V and AM2 X2s are typically up to 1.35V.
The only major exception is the 35W X2 3800 rated at 1.025/1.075V. But those are specialised low volume parts so hardly indicative of anything.


AMD / IBM and Intel use different technology for their chips.
a b à CPUs
August 29, 2006 2:22:11 PM

Quote:
hit our tender ears about what AMD's problems at 65nm are rather than

the nebulous 'they have issues'. A bird has been singing to us that AMD is having problems getting

the speeds they need out of the stock voltages.
This is forcing AMD to pump things as high as 1.4V. If you do the math, (1.4^2)/(1.1^2) = 1.62, so

AMD is forced to use 60+% more power than they wanted to. This kind of skews the performance per

watt leadership they are claiming, so I guess there is still work to be done.

That said, there is a bit more than three months to go before any deadlines are missed, and the

wafers going in today are still not the ones you may end up buying, so there is time. Barely.

µ


http://www.theinquirer.net/default.aspx?article=33964

Can somebody - above 12 - elaborate how going 65nm increases power consumption? Or this is just

another BS from edited?!

,,

I will politely answer you question but before I do I must respectfully request you PM the mods and lock the thread.

The Inquirer in this case is sporting a particuarly serious rumor that is just that--a rumor. Kukito had started a thread as such and I believe now as I did then that this is a subject best discussed with news that is more credible than Charlie D. from the Inquirer.

To be fair, when 9-inch posts something this out of left field he gets pounded and the mods lock it anyway. Let's be fair and hold off discussion until we are certain there is an issue.

Now to your question, it is a complicated one to answer, I have basically answered a similar question here:
http://forumz.tomshardware.com/hardware/modules.php?nam...

Here is essentially how it works. Companies scale transistor down by a fixed factor, which has historically always been 0.7 of the last generation. Sensible, as a viewing top down, a transistor has 2 dimension taking up area, thus 0.7*0.7 scaling on both sides yields 0.49 or about 0.5, i.e. 1/2 the area of the prior generation. That is why at 65 nm is about 0.7 of 90 nm, and is also why each node transition rougly 1/2s the die size (or consequently allows more transistors).

That 0.7 scaling doesn't stop in the area, it applies to all the inputs of the device, and, at constant voltage scaling all things being equal --- no new materials, all thickness and dimensions change the same --- the resulting transistor should theoretically perform exactly the same in speed and power DENSITY (i.e. watts/area) as the prior generation; note, because the size decreased, the overall power consumption decreases.

Unfortunately, that scaling assumes voltage scaling follows as well, and that the frequency stays the same --- in reality, this is not always true. Thus, engineering is required to increase the output parameterics that make up the transistor, the primary measured parameteric is called Idsat
or the saturated drive current. However, to get frequency up and Idsat up to target levels, if you made a mistake say in tweaking out the gate oxide, you may need to apply more voltage, more voltage increases the power consumed by the square of the voltage. That is why at the moment, based on this 'rumor' power can be higher than desired. This was also evident in the IEDM data AMD presented, the power and leakage at any voltage higher than 1.1 volts increases dramatically, the IEDM data also shows a slower transistor than Intel's, at the same stage depth of the
pipeline; thus I would expect release speeds to be slower than Intel's.

Here are some useful scaling links:
http://www.cs.technion.ac.il/~mendlson/l7-circuit/Desig...

http://www.eecs.berkeley.edu/~hu/PUBLICATIONS/Hu_papers...

http://www.sigda.org/Archives/ProceedingArchives/Dac/Da...

http://www.andrew.cmu.edu/user/rhussin/Research/Paper3....


Jack

Woah there,

Why lock a thread? Why not discuss it? Why must we support censorship? The US Government doesn't censor Fox News now do they? (largest network that posts FUD, mis-information and re-writes history for the benefit of the Republican agenda).

Get it straight. Democracies.. the free world does not, in essence, support censorship just because they're not pleased with what they hear. We can protest, we can discuss and we can argue/counter-argue. We truly do not know if AMD is having problems. We cannot dismiss this and claim that they're not having problems as that too would be FUD since we don't know.

So we meet the accusations head on and we try our best to discuss the issues using our own collective knowledge to try and best find a collective agreement as to the validity of the information put forward.. in this case the Inquirer.

I call on the mods to encourage more open debate, encourage democracy to live on even in this forum. Afterall, isn't Tom's Hardware a democratically alligned website? (they're from Germany no?).

Open Debate my friends... DO NOT LOCK THIS THREAD.


PS. Intel did have issues with leakage, it was there first Prescott series using a 90nm process. But the leakage was intentional in order to keep the cores stable. It ended up being the worst disaster of a CPU launch in recent memory. They fixed this of course when they shrank to 65nm, but I still remember the crappy Prescott.
August 29, 2006 2:52:21 PM

I vote to not lock the thread. Jumpin Jack has provided some good information that deserves to be bumped.

Thanks again Jack. *thumbs up*
August 29, 2006 3:04:00 PM

Democracy? Fox News? What? First off, I don't see the US Government shutting down CNN for spreading liberal agenda/propaganda either. But that's hardly the point of this thread.

On topic: Very informational response Jack. Thanks for the info.

My 2 cents - I think a thread like this should only be locked if it turns into a fanboy thread. If people like yourself are willing to post actual informational stuff then let the conversations continue.
August 29, 2006 5:16:43 PM

Quote:
Isn’t the whole idea that AMD’s 65nm desktop chips were ever intended to run at 1.1V questionable in the first place?
That seems too low when you look at current voltages for Intel at 65/90nm and AMD at 90nm. Conroe is rated up to 1.325V and AM2 X2s are typically up to 1.35V.
The only major exception is the 35W X2 3800 rated at 1.025/1.075V. But those are specialised low volume parts so hardly indicative of anything.


AMD / IBM and Intel use different technology for their chips.I know, that’s why I quoted separate figures for AMD and Intel.
But still, is there any official or even unofficial data showing that AMD ever announced that their 65nm parts will run at 1.1V?
Is the very idea of 1.1V in itself speculation?

Oh gosh, I’m speculating, the Mods are gonna come over to my house and bust a cap in my ass. :roll:
August 30, 2006 8:52:34 AM

Quote:
Well, no offical announcement as of yet, Intel's I believe is at 1.2 or 1.25 --- one thing is certain, it must be lower than 1.35, which is the mid point of AMD's current 90 nm specs.
Intel are currently using up to 1.3525V with Core 2 Duo including the X6800; Intel Spec sheet.
You can use less than that at lower clock speeds; I’m using 1.168V at 2.4GHz at the moment, this is set manually with RMClock. But when you go for around 3GHz you usually need 1.3V or more. My E6400 is rated at 1.325V which seems quite typical for C2D.

Back to the AMD thing; it doesn’t seem improbable that AMD might currently need 1.4V to hit say 3.2GHz. They probably don’t need to get it below 1.35V at 3.2GHz anyway to call it a success. This is speculation of course.

I still don’t buy the 1.1V idea. If you look at all the recent moves to a smaller process from both companies, we aren’t seeing a major drop in the VCore used. I thought that this would happen and it would be this that would lead to the lower power consumption for the smaller processes. But this doesn’t seem to be the case at all, at least as far as I can tell.
August 30, 2006 10:46:10 AM

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Effectively what you see here is a 90 nm Pentium-M clocked to the same speed as an FX-60 (over clocked), and a 70 watt difference, and a whopping 156 watt difference over prescott. I am comparing run of the mill CPUs with P-M matching FX-60 in clock-- stable and benchmarked. How can this mean 90 nm is leaky? It does not compute :) 
You are comparing a single core mobile CPU to a desktop dual core CPU in power consumption? :?
August 30, 2006 12:06:52 PM

Quote:
PS. Intel did have issues with leakage, it was there first Prescott series using a 90nm process. But the leakage was intentional in order to keep the cores stable. It ended up being the worst disaster of a CPU launch in recent memory. They fixed this of course when they shrank to 65nm, but I still remember the crappy Prescott.

Prescott was not bad becouse of the used process. As JJ described, Prescott failed becouse of its unefficient architecture. The double clocked ALU, produces extra heat(& consumes extra power). Becouse the ALU is clocked different, another clock generator is required and extra logic(more transistors) is involved. Hyper threading is another transistor waste, some parts of the CPU are doubled. Becouse of the slow FSB and slow memory sub-system, Prescott is equiped with a "lot" of L2 cache(compared to K8) - another transistor and power waste. So it is not becouse of the 90nm bulk, but is is the becouse of the bad architectural design, why Prescott was such a power waste.
The bad architecture(long pipeline) is the reason for its poor performance/clock efficiency, but that is another story about the bad Netburst crap.
August 30, 2006 10:57:00 PM

Quote:
Is AMD ashamed of showing 65nm ES?!


In a word... yes! Engineering Samples are nothing to be proud of, when it comes to the Inq.


Cheers!
August 30, 2006 10:59:28 PM

The United States is not a democracy. Just thought I'd clear that up.
August 30, 2006 11:25:36 PM

Quote:

I will politely answer you question but before I do I must respectfully request you PM the mods and lock the thread.

The Inquirer in this case is sporting a particuarly serious rumor that is just that--a rumor. Kukito had started a thread as such and I believe now as I did then that this is a subject best discussed with news that is more credible than Charlie D. from the Inquirer.

Jack

I disagree. Maybe it's because of my libertarianism, but I don't believe you should be imposing limits on debate based on what you believe is appropriate or not. It's not up to you. That's what the moderators are for. In the meantime, just say what you believe is an appropriate response to the post, but don't try to use your clout to bully people into censoring themselves.
August 30, 2006 11:32:40 PM

It's a community forum, shaped by both moderators / admin and community alike. Jack may be voicing an opinion, but it should be a valued one based on the amount of time he has devoted to the community and the quality of his input.

Ironically, you're imposing limits or rather boundaries by raising the issue of what you perceive as someone else's limits on the forum and thus in exactly the same position, i.e. one of opinion.
August 30, 2006 11:44:15 PM

Quote:
Ironically, you're imposing limits or rather boundaries by raising the issue of what you perceive as someone else's limits on the forum and thus in exactly the same position, i.e. one of opinion.
Well said.

Quote:
It's a community forum, shaped by both moderators / admin and community alike. Jack may be voicing an opinion, but it should be a valued one based on the amount of time he has devoted to the community and the quality of his input.
I don’t see that a forum member’s posting record in terms of technical posts in regard to quality or quantity has any bearing in this matter though. We are talking about a non technical matter here and a posting from a technical ignoramus or a first time poster holds just as much sway surely! Don’t mistake technical competence for competence in any other areas, or allow familiarity with a person to cloud your objective perception.
August 30, 2006 11:51:04 PM

Quote:
This is one more example with instigating rumors such as this without good proof, a brief statement of mole digging run amuck --- the Inquirer should be shut down completely.

Jack

Authoritarianism and censorship suck. AMD is within its rights to sue the Inquirer, and laws in the UK are much more permissive in this regard than in the USA. If you ever become a moderator in this forum I'll be the first to head out the door instantly.
August 30, 2006 11:57:56 PM

Quote:
Ironically, you're imposing limits or rather boundaries by raising the issue of what you perceive as someone else's limits on the forum and thus in exactly the same position, i.e. one of opinion.

Bullcrap. I have never told anyone in this forum to self-censor. I'm not the one requesting people to close their own threads.
August 30, 2006 11:58:09 PM

Quote:
(...) yet people infer a leaky Intel 90 nm process based on what they observe from the behavior of Prescott becaues they do not understand the importance archtecture has on power consumption. P-M has 12-14 stages (very much more K8 like) and Netburst had 31 --- long pipelines consume more power, it is a true statement.


My observation will be somewhat iconoclastic but, anyway:

Given the above said, if & when a new process shift arrives (like trigates & new materials), wouldn't it be reasonable to (re)increase pipeline stages in order to (re)increase speed? Isn't it somehow implicit that, shifting the process will also force a shift in the microarchitecture & vice-versa? (not a "simple" node transition, of course).

Some requirements:

a. The resulting transistors are less leaky & consume less power;

b. 3D features follow the same physical formulas :roll: : (Cg*Vdd/Idsat or, perhaps, a return to Idsat~W/L*u*Qinv, etc...);

c. Overall TDP is not incompatible with multi-core/single-die (seems to be the trend...)


Bottom line: Could we be seeing a "NetBurst-like" microarchitecture, take 2, as a mid-term possibility?


Edit: Boy, much has been worded while I was writing this post...



Cheers!
August 31, 2006 12:00:56 AM

Quote:
Ironically, you're imposing limits or rather boundaries by raising the issue of what you perceive as someone else's limits on the forum and thus in exactly the same position, i.e. one of opinion.

Bullcrap. I have never told anyone in this forum to self-censor. I'm not the one requesting people to close their own threads.

No, you're not. You're the one that is insisting on them being kept open no matter what. Read carefully the postings before jumping on this.
August 31, 2006 12:18:00 AM

Quote:
No, you're not. You're the one that is insisting on them being kept open no matter what. Read carefully the postings before jumping on this.

Again, you're trying (unsuccesfully) to turn my own words against me. I only propose that the mods keep doing what they do well, intervening only when they deem it necessary. Like I said, if JJ becomes a moderator, I will gracefully bow out because I disagree with his authoritarian style. I'm not attempting to impose limits on JJ's speech or anyone else's, just voicing an opinion.
August 31, 2006 12:19:48 AM

Quote:
Woah there,

Why lock a thread? Why not discuss it? Why must we support censorship? The US Government doesn't censor Fox News now do they? (largest network that posts FUD, mis-information and re-writes history for the benefit of the Republican agenda).

Come Come! Lets not forget the 5 second delay. We could have a Janet Jackson even in the news rooms.

Quote:
Get it straight. Democracies.. the free world does not, in essence, support censorship just because they're not pleased with what they hear. We can protest, we can discuss and we can argue/counter-argue. We truly do not know if AMD is having problems. We cannot dismiss this and claim that they're not having problems as that too would be FUD since we don't know.

Please one 9-inch to many :!: Could we have a new 9-inch here? Sorry, for the mud slinging, ElMoIsEviL but supporting Inquirer is a bad move. Its not censorship as Inquirer has it for the whole world to see. Keeping the forum from going down to Inquirers level is, I think, JumpingJack reason for locking the thread.
August 31, 2006 12:43:22 AM

Quote:
Please one 9-inch to many :!: Could we have a new 9-inch here? Sorry, for the mud slinging, ElMoIsEviL but supporting Inquirer is a bad move. Its not censorship as Inquirer has it for the whole world to see. Keeping the forum from going down to Inquirers level is, I think, JumpingJack reason for locking the thread.

But that's precisely the point. JumpingJack does not have the authority to lock threads, which is why he suggests that we contact a moderator to get it done.
August 31, 2006 12:44:17 AM

I'm not saying the 90nm process was "leaky", I'm questioning why you chose to compare a single core mobile processor to a dual core desktop CPU. Even if only one thread is being used, the second core on the FX60 is still consuming power. :?

Now a better comparison would be comparing a 2.8GHz 90nm Pentium D to a 2.8GHz FX60. :wink:
August 31, 2006 1:13:44 AM

So far I haven't seen any transition to lower process where one had to increase voltage. It should at least stay the same regardless of added features because transistors should be more efficient.
August 31, 2006 1:16:21 AM

Quote:
I'm not saying the 90nm process was "leaky", I'm questioning why you chose to compare a single core mobile processor to a dual core desktop CPU. Even if only one thread is being used, the second core on the FX60 is still consuming power. :?

I think the point he's trying to make is that Intel's process is not inherently "leaky" and that the Pentium M proves that point.
August 31, 2006 1:24:21 AM

Quote:
AMD's 65 nm process is much more than simply a shrink of the 90 nm process, sure maybe masks are a shrink but the process itself contains 3 new stressing techniques, a shallower surface Si overlayer, and due to embedded SiGe a new silicide for contact formation (likely NiSi).


EETimes had an article a few years ago:
AMD may bring in metal gates at 65-nm node

Quote:
AMD calls its fully silicided approach FUSI. The source and drain region is protected by a silicide layer, and then the polysilicon gate is completely converted to a NiSi metal, all the way down to the gate oxide. The metal composition can be tuned to support the required work function (the energy required to move electrons and holes) for NMOS and PMOS devices, something that is much more difficult to do with deposited metals, Xiang said.


The industry has yet to identify which metals could provide the right work function for CMOS devices, or how to create a process flow for deposited metals, so the FUSI approach may be the only practical approach at the 65- and 45-nm nodes.


Nice read for any out there who think that the shrink to 65nm is just a simple matter of making the die smaller.
August 31, 2006 1:29:42 AM

Quote:
I think the point he's trying to make is that Intel's process is not inherently "leaky" and that the Pentium M proves that point.
It shows that a single core consumes less energy than a dual core CPU. But yeah, Intel's process is not "leaky".
August 31, 2006 2:57:27 AM

Jack, I agree with your view of not basing a thread off of such a negative rumor when there is no evidence yet either way but this thread itself wasn't started saying "look at all the problems AMD is having" is was started on the basis of "there is this rumor and I don't understand how what is says is true is possible does anyone know" If it was started as just "look at this article it says whatever about AMD" (it doesn't matter if it is negative as in this case or some super good thing 9-inch posts) then I could understand locking the thread but this was started as more "I don't understand this help me" which is the kind of thread that I enjoy following as long as it stays on topic and we can keep the insults out of it.
August 31, 2006 2:59:44 PM

Quote:
Please one 9-inch to many :!: Could we have a new 9-inch here? Sorry, for the mud slinging, ElMoIsEviL but supporting Inquirer is a bad move. Its not censorship as Inquirer has it for the whole world to see. Keeping the forum from going down to Inquirers level is, I think, JumpingJack reason for locking the thread.

But that's precisely the point. JumpingJack does not have the authority to lock threads, which is why he suggests that we contact a moderator to get it done.
True, my grammer sucks, I should have stated it diffently. Maybe this would have been better.
Quote:
Its not censorship as Inquirer has it for the whole world to see. Keeping the forum from going down to Inquirers level is, I think, JumpingJack reason for wanting the thread locked.

Sorry for the confusion.
August 31, 2006 3:22:42 PM

Quote:
True, my grammer sucks, I should have stated it diffently. (...) Sorry for the confusion.


Much, much better, though; I still remember when JumpingJack mentioned English wasn't, probaly, your native language; and, I thought you had a deeper problem still! :D 

I had no trouble understanding what you meant, even if grammar isn't your forte.


Cheers!
August 31, 2006 9:04:46 PM

Quote:
Is AMD ashamed of showing 65nm ES?!


In a word... yes! Engineering Samples are nothing to be proud of, when it comes to the Inq.


Cheers!

Well I guess you were under a rock when Conroes ES were around...
August 31, 2006 9:17:26 PM

Quote:

I will politely answer you question but before I do I must respectfully request you PM the mods and lock the thread.

The Inquirer in this case is sporting a particuarly serious rumor that is just that--a rumor. Kukito had started a thread as such and I believe now as I did then that this is a subject best discussed with news that is more credible than Charlie D. from the Inquirer.

Jack

I disagree. Maybe it's because of my libertarianism, but I don't believe you should be imposing limits on debate based on what you believe is appropriate or not. It's not up to you. That's what the moderators are for. In the meantime, just say what you believe is an appropriate response to the post, but don't try to use your clout to bully people into censoring themselves.

Perhaps I should re-explain myself.... it's not tht the topic is not worthy of discussion and that it should not be open for discussion. It is the means at which the topic has been brought to us, and a desire to be fair before we jump into a long argument about this, that, and the other. Honestly, I appreciate you stepping up and agreeing to shut it down, but now that this thread was created --- I wish we could go back and bump your's up and shut this one down, mainly because yours was more tactfully and tastefully presented overall. Look at the title for goodness sake :)  .

Now there are many reasons what I say this, and please continue to disagree because this is a better debate than on the actual topic.

I actually have nothing against a good juicy rumor post and the debate, sometimes heated that can go around it, 99% of the time it is more or less harmless. But 65 nm for AMD is a more sensitive topic and my opinion is that AMD deserves the benefit of the doubt, or at least until the rumor can be corroborated with a more credible source. Why, just to be respectful to a company that is working hard and to the engineers that we all know are bustin' butt to make it work. Also, Fab 36, 4x4, FX-64, etc. etc. all fluff in comparision to the importance 65 nm is to AMD, without 65 nm no quad core, any new architecture to compete is delayed or dead.... the health of AMD over the next 12-18 months hinges on successful development of 65 nm. I am 100% certain they will do it, thus I do not take this rumor as fact.

Finally, 99% of the Inq posts that come onto the Forum is anti-Intel or pro-AMD and offers very little value to the forum other than to create fanboy posts and 10 pages of nonsensical arugments. As such, many Inq posts get locked down anyway. The majority of those being 9-inch postings, of course, which I track and shame him at every opportunity. At least he is not posting Inq articles any more. THForumz is not an Inq mirror.

Now one cannot argue to shut down those links without arguing to shut down this topic as a basis of innuendo and fanboyism and remain objective. If 9-inch, or other Inq posters get locked up, then the same standards must apply. This is not an "Intel forum" as 9-inch would so eloquently (actually non-eloquently) want you to believe, so I advocate 'let the data speak'. As such, we will know either by second sources or simply 'no 65 nm parts in Dec' if AMD is really having issues.

If you are really interested in a good discussion, start another thread or bump one of the many 'what issues would AMD likely face with 65 nm on SOI', and keep it away from rumor realm.

Nonetheless, I do appreciate your original effort myself as I still think you did the right thing --- once we know yes they are falling behind on 65 nm or no they are not, then we can address it --- but again, the Inq is not the best source of information.

Jack

I didn't get it then. are you pissed off ( unhappy maybe?) because the source is Inq or because the thread is a re-run?! In either case there is not much to do unless you make the original thread a sticky or take the Inq site down.

,,
August 31, 2006 9:26:31 PM

Quote:
Thanks --- I think Elbert above summed up my longer post in a more concise way, some rumors are fun to talk about the Reverse Hyperthreading was actually cool --- and forced me to read up on threading and multi-tasking in general.

@ Elbert --- you pretty much are right, gossip and rumor is best left to supermarket tabloid racks.

Jack

True and even if the Inquirer is correct ever new process level has its wrinkles to fix. AMD has went though this process nearly as many times as Intel. The fact is AMD and IBM does joint research which, IMO, places AMD more capable to fix any problem than Intel.

The big problem I have with Inquirer is what information is given? What chips are they talking about? Is it quad or dual core? Is it Opteron or X2? Maybe Its K8L! If its the X2 then home users want care much. If its Opterons then we have a problem which could take a extra month.

We have a nice little save all statement at the bottom.
Quote:
That said, there is a bit more than three months to go before any deadlines are missed, and the wafers going in today are still not the ones you may end up buying, so there is time. Barely. µ

Its like saying Intel has a problem hitting 3.33GHz with Core 2 Duo due to Intel cutting the X6800 down to 2.93GHz. It a process nothing more. True it takes time and a lot of money, money I wish I had, but in the end we are talking about a small set back if that.

Reverse Hyperthreading was fun and I wish everyone could see the problems with Inquirer as we do Jack.
August 31, 2006 9:28:32 PM

Quote:
I will politely answer you question but before I do I must respectfully request you PM the mods and lock the thread. …..

I didn't get it then. are you pissed off ( unhappy maybe?) because the source is Inq or because the thread is a re-run?! In either case there is not much to do unless you make the original thread a sticky or take the Inq site down.,,
Jumping by name, jumping by nature!

It’s the thin end of the wedge, before you know it these forums will be moderated by representatives of Google China. “It’s the party line or the end of the line.”
Free Tibet, free The Inquirer.
September 1, 2006 12:38:12 AM

Quote:
Is AMD ashamed of showing 65nm ES?!


In a word... yes! Engineering Samples are nothing to be proud of, when it comes to the Inq.


Cheers!

Well I guess you were under a rock when Conroes ES were around...

As much as the Inq. itself. You guessed right.


Cheers!
September 1, 2006 1:24:14 AM

Oh really? I didn't know that AMD is shy like that.
September 1, 2006 2:30:31 AM

It seems to me that I remember way back reading something Intel said about SOI... I seem to recall something along the lines of SOI is good at 90nm's but at smaller nodes it could cause problems. Perhaps this is what Intel knew all along ? I think it had something to do with capacitence causing higher resistance and therefore causing more heat buildup. I probably should try to find the article but im a very lazy person lol

Edit:I decided to google around a little and it does seem Intel predicted some problems with SOI in the smaller node and also that it is more expensive... It is about 10% more expensive and leads to lower yields !
here is some of what I found (I read alot more then this one but this one seemed to be the most complete with the pro's and con's)
http://www.eet.com/story/OEG19990618S0013
September 1, 2006 10:43:06 PM

Quote:
Intel ran a development line on SOI to evaluate the capability. They did this back in 2001-2002.

http://www.stanford.edu/class/ee311/NOTES/Intel_30nm.pd...

I have posted this before, you will see in Fig. 23 about 2/3rds into the article, a SEM picture of the transistor they build using stress liner, embedded SiGe, and SOI -- essentially the transistor AMD is trying to get into production today at 65 nm (The did this in 2001, published in 2002).

Thats was amazing. I found IBM currently working below 10nm at around 1.5nm which is equally amazing.
http://news.zdnet.co.uk/0,39020330,39280735,00.htm
For over a year now IBM has been working on the 20-25nm hard stop point, the point where circuits couldn't get any shorter.
http://www.dgl.com/itinfo/2000/it000811.html
I bring this up for 1 reason, while SOI may have lost its half a generation advantage, soft errors may be a better reason for SOI today.
Quote:
He did agree, however, that SOI does have an advantage in preventing soft errors, an issue that has recently become a bigger concern for Intel as it scales its process technology below 0.25 micron. SOI is two to three times better than bulk silicon in preventing soft errors, which "may in the future be an argument for SOI," Bohr said.

SOI's advantage in soft errors was never tested by Intel and may only have begin to have an impact at 45nm. By way of V-groove and SOI, IMO, Intel may have to pay the piper.
September 2, 2006 1:22:11 AM

Quote:
Intel ran a development line on SOI to evaluate the capability. They did this back in 2001-2002.

http://www.stanford.edu/class/ee311/NOTES/Intel_30nm.pd...

I have posted this before, you will see in Fig. 23 about 2/3rds into the article, a SEM picture of the transistor they build using stress liner, embedded SiGe, and SOI -- essentially the transistor AMD is trying to get into production today at 65 nm (The did this in 2001, published in 2002).

Thats was amazing. I found IBM currently working below 10nm at around 1.5nm which is equally amazing.
http://news.zdnet.co.uk/0,39020330,39280735,00.htm
For over a year now IBM has been working on the 20-25nm hard stop point, the point where circuits couldn't get any shorter.
http://www.dgl.com/itinfo/2000/it000811.html
I bring this up for 1 reason, while SOI may have lost its half a generation advantage, soft errors may be a better reason for SOI today.
Quote:
He did agree, however, that SOI does have an advantage in preventing soft errors, an issue that has recently become a bigger concern for Intel as it scales its process technology below 0.25 micron. SOI is two to three times better than bulk silicon in preventing soft errors, which "may in the future be an argument for SOI," Bohr said.

SOI's advantage in soft errors was never tested by Intel and may only have begin to have an impact at 45nm. By way of V-groove and SOI, IMO, Intel may have to pay the piper.

Quote:
"The maximum switching speed depends very much on the mechanism which is used for switching," Dr Riel said. "The switching time is at least faster than 640 microseconds. However, we cannot give an upper limit yet." She said that this would depend on future investigations into how it worked, and that tests done on a similar molecule conclusively narrow the active area of the device down to a very specific area.

The experiment itself mounted the molecule between two gold electrodes that could be adjusted to sub-picometre accuracy. Although most of the testing took place under extremely cold conditions, some results showed that the molecule continued to switch states at room temperature — although, as the gold was then much softer, it flowed and short-circuited after a few cycles.
At around 1.5nanometres (nm) long, the molecule is less than one-hundredth of the size of current silicon memory elements. It is widely accepted in the industry that current progress in silicon will become economically more difficult below 20nm, with fundamental physical limits being reached below 10nm. IBM says it sees molecular computing as one way of pushing past this barrier, as well as semiconducting wires, carbon nanotubes and spintronics.


I knew this would become an interesting thread, afterall... not my fault , though! :wink:

I haven't got the time, now; anyway...

http://www.ccm.udel.edu/Pubs/05Posterbook/UG/Schmalz_AThree-Dimensional_Poster2004.pdf#search=%22v-groove%20channels%22

and, "the devil is in the details" (there are a lot of detailed articles on molecular computing, CNT, spintronics, Quantum Computing & such, speculation aside).

http://nanotechweb.org/articles/news/5/9/3/1?rss=2.0


Cheers!
September 2, 2006 2:09:51 AM

Quote:
Elbert -- dude, let me compliment you on a great and high octane post, great contribution -- I will come back with my inputs, don't have a great deal of time right now. But nice work.

Jack

Thanks Jack,
I do summit this could all change in very little time but it points out the problem with the thread. The unknown future. Got to love the complexity.

Can Intel force IBM to license SOI and V-groove? IBM could be in a fix, ending up having to license to their competition, for licensing to AMD. I love it and at the same time this is giving me a headache.
September 2, 2006 2:36:38 AM

Quote:
Elbert -- dude, let me compliment you on a great and high octane post, great contribution -- I will come back with my inputs, don't have a great deal of time right now. But nice work.

Jack

Thanks Jack,
I do summit this could all change in very little time but it points out the problem with the thread. The unknown future. Got to love the complexity.

Can Intel force IBM to license SOI and V-groove? IBM could be in a fix, ending up having to license to their competition, for licensing to AMD. I love it and at the same time this is giving me a headache.

Intel and AMD already have good cross liscencing deals if Intel wanted too they could make SOI chips tomaro. I would say that Intel feels that SOI will be replaced by something better before it realy becomes something that is required. I do know from what I have read that SOI has advantages but it also has some drawbacks.(thanks to all that posted such interesting reading material !!!)

Edit:Im not sure what V-Groove is, that could be something that IBM has a patent on and I am not sure about IBM and Intels relationship in that respect. SOI I think is more a type of silicon, like strained or back in time doped. I guess they just deposit some insulation on the wafer and etch from there (very over simplistic ?) Im waiting for those plastic chips, I want talking singing cereal boxes now !!! lol
September 2, 2006 1:02:39 PM

Quote:
I wish everyone could see the problems with Inquirer

the_INQ has no problems! But those who are folowing the_INQ have problems for sure. For example 9nm, BaronBS, LMM and other derivates from Shakira
September 2, 2006 2:02:09 PM

Quote:
I wish everyone could see the problems with Inquirer

the_INQ has no problems! But those who are folowing the_INQ have problems for sure. For example 9nm, BaronBS, LMM and other derivates from Shakira

I always say I like the Inq but I hardly ever say I take them at face value :)  (Those papers that print the stories about Bat Boy robing the local blood bank have the same level of reputation lol)
September 2, 2006 2:46:38 PM

Quote:
Intel and AMD already have good cross liscencing deals if Intel wanted too they could make SOI chips tomaro. I would say that Intel feels that SOI will be replaced by something better before it realy becomes something that is required. I do know from what I have read that SOI has advantages but it also has some drawbacks.(thanks to all that posted such interesting reading material !!!)

Should be IBM but yes they could have licensed SOI. The question here is has Intel, by stealing away the Apple platform, stepped on IBM enough for them to resist the licenses?
Quote:
IBM is a recognized innovator in the chip industry, having been first with advances like more power-efficient copper wiring in place of aluminum, faster silicon-on-insulator (SOI) and silicon germanium transistors, and improved low-k dielectric insulation between chip wires. These and other innovations have contributed to IBM's standing as the number one U.S. patent holder for 10 consecutive years. More information about IBM Microelectronics can be found at:

http://www.apple.com/pr/library/2003/jun/23joint.html

The drawback is a higher cost to manufacture and to loss in yeild over Intels process.
Quote:
He concluded by saying SOI provides less than a half-generation performance gain, has too many circuit-design uncertainties, adds another 10 percent to the process cost for an extra mask step, requires pricier wafers and may lead to yield loss.

Many experts have stated going to 25nm is going to be costly as bulk silicon want be enough to stop the ever increasing soft errors. The cost will rise for Intel no matter if they use SOI and v-groove or another process.
September 2, 2006 3:10:34 PM

Quote:
Intel ran a development line on SOI to evaluate the capability. They did this back in 2001-2002.

http://www.stanford.edu/class/ee311/NOTES/Intel_30nm.pd...

I have posted this before, you will see in Fig. 23 about 2/3rds into the article, a SEM picture of the transistor they build using stress liner, embedded SiGe, and SOI -- essentially the transistor AMD is trying to get into production today at 65 nm (The did this in 2001, published in 2002).

Thats was amazing. I found IBM currently working below 10nm at around 1.5nm which is equally amazing.
http://news.zdnet.co.uk/0,39020330,39280735,00.htm
For over a year now IBM has been working on the 20-25nm hard stop point, the point where circuits couldn't get any shorter.
http://www.dgl.com/itinfo/2000/it000811.html
I bring this up for 1 reason, while SOI may have lost its half a generation advantage, soft errors may be a better reason for SOI today.
Quote:
He did agree, however, that SOI does have an advantage in preventing soft errors, an issue that has recently become a bigger concern for Intel as it scales its process technology below 0.25 micron. SOI is two to three times better than bulk silicon in preventing soft errors, which "may in the future be an argument for SOI," Bohr said.

SOI's advantage in soft errors was never tested by Intel and may only have begin to have an impact at 45nm. By way of V-groove and SOI, IMO, Intel may have to pay the piper.

Elbert, I am going to take a moment to explain soft errors for other readers who are unfamiliar.

Soft errors are generated when a bit is changed or flipped due to external causes such as radiation or other influences. They are in observed in the SRAM and typically are benign as single bit errors are corrected or caught during the ECC check on the cache as part of the load/decode phase.

The soft error rate is lower on SOI, I am guessing because I have not studied up on the subject, because the cause of soft errors, if generated deep in the substrate is guarded against by the buried oxide layer.

I believe Intel tested it as they did make devices and this is a pretty standard industry wide check. Soft errors are noted as a nuisance but can be problematic if the soft error rate goes to high. I have no data on the rate, but I have read that one soft error occurs every 3 to 30 days and are caught be the error checking mechanisms so I don't think it is a major concern (I have not read what this is on SOI nor do I have any recollection).

It is a good point though, SOI brings secondary benefits that are not publicized, this is one -- another is basically a second knob to tune what people call short channel effects (note it doesn't eliminate SCE, but it does give you another variable to tweak to help minimize it).

Jack
Thanks Jack,
I for one don't want AMD getting a big advantage on Intel or vis versa. Everyone wants cheap CPU's and Intel isn't just setting back waiting on 25nm. Intel has an answer for SOI but I'm not sure if it will answer V-groove's challenge. Intel's answer for SOI is Copper Doped Oxide (CDO) or as Intel calls it 'high k' material. High K will increase the costs of production but I dont think it will slow production as SOI does. One of the reasons Intel rejected SOI.
http://www.pcmag.co.uk/personal-computer-world/features...
!