Intel News Release
©2006 Intel Corporation

Intel Launches New Processors
Copyright 2006 Associated Press

http://news.zdnet.com/2100-9584_22-6110398.html

Intel claims, so take with a grain of salt. Hope Tom's gets a head to head comparison soon.

Sorry to be off topic, but is anyone having problems with the forum?

I keep getting errors, and find myself constantly closing my browser, and relogging in.

Is the forum being somewhat overhauled?

Yes! The database is FUBAR right now. It's been this way for 3+ days. It's a hit or miss thing right now.

I've reported it (constantly) to the webmaster and web developer. Don't know for sure what they're doing.

Been that way for the past few days. I can't even get to the Software section without an error.

Hopefully bigger things are afoot. :?
Maybe they're replacing servers with Tulsa ones. 8)

Here are some SAP-SD benchmarks with Tulsa versus Opteron:

IBM X3950 Xeon 7140N 8S/16C/3.33GHz/667FSB: 3350 users
Fujitsu-Siemens BX630 Opteron 880 8S/16C/2.4GHz: 2170 users

HP DL580 Xeon 7140M 4S/8C/3.4GHz/800FSB: 2127 users
Sun Blade x8400 Opteron 885 4S/8C/2.6GHz: 1700 users

http://www50.sap.com/benchmarkdata/sd2tier.asp

One thing that troubles me about these new server chips (I'm not advocating anything, unlike some we know here) is what is being reported in TG Daily today:

Intel refreshes Xeon MP series with new Tulsa processors
© 2006 Tom's Guide Publishing.

I was under the impression that Intel was trying to get away for Netburst - and now they introduce a new server line based on Netburst? Maybe the 65 nm production process will make a difference. Still, I find this odd.

Maybe one of you guru's can explain this?

It takes time for validation. And a big cache, SMT and good quality chipsets can overcome architectural deficiencies. Tulsa paired with IBM's X3 chipset should be the top performing 4S+ x86 server in nearly all server benchmarks.

At least until the Core based MP processors arrive.

It's really an increased cache, stop-gap chip until they release Tigerton next year. It's a drop-in upgrade for Paxville platform. Seems like a good solution for the 4-socket&up server space.

As others have mentioned stability is critical for Xeon MPs so they are usually the last to transition to any new technologies after they have been tested in other product lines.

The major roadblock to using Core 2 for Xeon MP is the lack of motherboard and chipset support. I don't think the current motherboards meet the correct VRM standards which means that everyone would have had to buy a completely new system. Using Netburst allowed Tulsa to be a drop-in replacement. The other option would be to do a refresh with new VRMs on the current chipsets like what was done to the i975X, but that would have been a disaster. The current chipsets only support up to 2 800MHz FSBs for 4 sockets which is even less than the 2 1333MHz FSBs of Bensley.

Intel is working on a new chipset with the Truland platform using quad FSBs, which should be a great benefit. Still, I think the chipset is still lacking in implementation. The current design calls for 4 1067MHz FSBs coupled with a 6 channel DDR2 667 FB-DIMM memory controller. This isn't sufficient for Tigerton which is a dual die quad core chip. (THG is wrong BTW since they say Tigerton is a dual core chip). The preferred configuration to me would be either 4 1333MHz FSBs with 8 channel DDR2 667 FB-DIMMs or 4 1333MHz FSBs with 6 channels of DDR3 800 FB-DIMMs. Since an 8 channel memory controller might be a bit difficult, the latter option would be easier to implement. The use of DDR3 memory would also drop power consumption which is idle. By the time Truland is released in around mid-2007, DDR3 should be available by then. Even if it isn't common, DDR2 800 could be used instead since the FB-DIMM architecture allows it to be used interchangably with DDR3.

In the end, Tulsa will still be useful since the software it'll be running will already be optimized for Netburst's architecture. Using Woodcrest as a test platform, by the time Tigerton arrives for Xeon MP, software optimized for Core 2 would be available that best takes advantage of it. This is especially true in 64-bit mode where you have to ensure that the average instruction length is 4 bytes otherwise you won't achieve the optimal 4 issue rate.