While clock speeds have not been revealed, each of the four cores will integrate 64 KB L1 Cache and 512 KB L2 cache. The native quad-core architecture will also include a 2 MB shared L3 cache, which may increase in capacity over time. The processor will have a total of four Hypertransport links - up from three today - that provide a total bandwidth to outside devices of 5.2 GB/s. AMD is also thinking about integrating support for FB-DIMMs "when appropriate."
my question is if one of the cores is not in use will the core resource go to waste like the Hyper Thread (HT) pipelines and L3 cache for that core not be used? or will the active core(s) be able to access the halted core(s) resourse for its own use? this also applies to the HT. if each core will have 4 HT pipelines each but only one core is active will that one core have full access of 16 HT pipe lines (4 cores with 4 HT each, hance 4x4)? but to make full use of the resources will all cores have to be active? will balance load the cores is the only way to take full advantage of the resources instead of one core running at 100%? i know AMD and intel has not disclosed any info about this. but i am wondering what people think will happen.
people talk about frontside bus bottle necks, how will intel and amd over come the bottle neck. we all ready know that flexible core clocking will help AMD reciece low wattage.
AMD's 4x4 be able to switch core clocks instantly? if a program requires all of a sudden to boost the CPU clock speed to quickly process an action. will AMD be able to adjust the core clocks speed fast enough to produce the the banchmark numbers efficiantly? benchmarks usually stress the cores abilities to see what it is capible of but not if the processor is efficiantly balance loading the work needed amoung the cores.
