Anand,
Viewing the specs for the EE vs non-EE they appear to by undervolting the EEs to achieve the lower power, and likely down-binning but it is not clear. Here is the comparision I would like to see:
EE vs non-EE at identical clocks and Vcore across a matrix, say take a 3800+ do a matrix:
2.0 GHz @ 1.20, 1.25, 1.30, 1.35
2.2 GHz @ 1.20, 1.25, 1.30, 1.35
etc.
Put it under full load and measure power and temperature (use the same thermal solution at the same fanspeed RMP), disable cool and quiet.
My suspicion is that they are doing more than simply undervolting and that there is a processing trick that is getting an extra 10%. For example, at 1.20 the dynamic power would only scale down about 15%, or roughtly 89 TDP to 75 TDP, another 10 watts needs to come from somewhere -- is it binned from frquency, is it a leakage trap/trick, could these be just super low yielding straing 90 SOI wafers?
Doing the skew above on both a non-EE and EE would allow one to determine where within the matrix of bin's AMD may be choosing the EE processors and why we have such low availability.
Thanks.