Sign in with
Sign up | Sign in
Your question

Intel Yorkfield Vs. AMD Altair (K8L)

Last response: in CPUs
Share
October 4, 2006 3:52:54 PM

Found some interesting information on Yorkfield. Yorkfield is a quad core composed of two 45nm Penryn die. Apparently it's out in Q3 2007.

http://www.vr-zone.com/?i=4109
October 4, 2006 4:48:16 PM

lol, true. Imagine an amd chip that could effciently use 12mb of cache :)  what would intel do then :D 
October 4, 2006 4:56:17 PM

Hmm...intel seems to be upping the clock and adding cache again, sound familiar?

It is hardly a "vs." article, its just a few details on intel's upcoming chip, and a scant mention of AMD at the end. Very misleading title.
Related resources
October 4, 2006 5:08:59 PM

Quote:
Very misleading title.


misleading, yes
but hey isn't half of journalism about drawing in readers :wink:
a c 471 à CPUs
a c 115 å Intel
a c 118 À AMD
October 4, 2006 5:32:22 PM

Hmm... 12MB of cache....

While great for databases, I doubt the typical user would benefit from even having 6MB of cache. I think there were even two conflicting articles about the benefits between 2MB and 4MB of cache.
October 4, 2006 6:14:07 PM

Quote:
Found some interesting information on Yorkfield. Yorkfield is a quad core composed of two 45nm Penryn die. Apparently it's out in Q3 2007.

http://www.vr-zone.com/?i=4109


Actually, I believe that vr-zone is mistaken about Yorkfield.

Conroe is a Native Dual-Core on 65nm with 4mb SHARED L2.
Kenstfield is the "glued" quad-core (same as Pentium D) part on 65nm, with two Conroe dies on the same PCB, and two L2 caches..

Yorkfield will be the Native Quad-Core part, on 45nm with a 12mb SHARED L2.

linky:
http://digitimes.com/bits_chips/a20060928A2007.html
http://www.theregister.co.uk/2005/12/05/intel_45nm_road...
Anonymous
a b à CPUs
October 4, 2006 7:40:05 PM

Who cares about the amount of cache on a processor, 12 meg says a lot about the Core 2 architechture, thats is: lot's of cache with smart logic can negate the effects of the aging FSB interconnect... Also why put this much? cause they can! and it's good for marketing!

Amd could'nt make good use of that much cache because they went another road with their design. The ODMC is more elegant I agree but as long as you get results( performance/price ,performance /whatt, etc) who care how it's done!

Amd did'nt go down that path because they dont have the technology Intel has to cram that much Cache, that might change with Z-Ram and then who knows, maybe they will have 64meg of L2 but then again they might be fine with 1 meg...
October 4, 2006 8:18:07 PM

Quote:
That Intel feels they need 12mb of L2 on their quad 45nm to compete with AMD's quad 65nm part says a lot.
Its actually ridiculous if you ask me. Whats next 24mb of L2? I havent even gotten to 512 yet!! 8O :lol: 


Let me think... Got it: FANBOY AT WORK!!! :evil:  :evil:  :evil: 

What do you care about Intel adding more cache to their cpu as long as it deliver on performances front???? Cache just happen to be one of Intel strengh (as oppose to AMD who's latency generally get's worst than Intel when bigger), so why not use it. These guys ask themself if more cache will bring the performances gain worth the extra die space. If so they use it. Plain and simple!

AMD, on the other hand, is way more "Fab limited", so they can't afford to play that game. And I get their point too, that's how they survive and managed to gain 20-30% of overall x86 cpu shipment.

In a better world, AMD would have more Fab space and Intel would use on-die memory controller with Hyper Transport 3.0. It's only that neither does for now... but all will eventually, so stop whining :twisted: .

As for me, I'll use any CPU that deliver on the performances front at the price I'm ready to pay. You should do the same!!! :idea:
Anonymous
a b à CPUs
October 4, 2006 8:21:14 PM

Itanium 2 Montecito has 24 meg, must be marketing....
Anonymous
a b à CPUs
October 4, 2006 8:53:47 PM

They're working on Common System Interface(CSI).

HT is actually open and not proprietary to AMD
Wiki will tell you that!

Only thing to that is proprietary to AMD is HTc (with cache coherency) used to interconnect CPU's.

(thanks to whoever posted that a while ago can't remember :oops:  )
October 4, 2006 9:13:46 PM

Quote:

All I can say is all that cache is gonna cost money. Hope it's worth the price.


Cache is actually _less_ expensive than random logic. A large cache can be made redundant and will improve yields of a chip and lower prices.

A 12MB cache on 45nm is actually 33% smaller than the 8MB cache on 65nm in Kentsfield. So in relation to Kentsfield, the cache is smaller ;) 

Intel's chips benefit from such a cache because of the FSB interface. They're a bit farther away from memory. They compensate with the large cache and specialized stream prefetchers.

EDIT: changed 50% to 33% ;) 
October 4, 2006 9:43:38 PM

Quote:
That Intel feels they need 12mb of L2 on their quad 45nm to compete with AMD's quad 65nm part says a lot.
Its actually ridiculous if you ask me. Whats next 24mb of L2? I havent even gotten to 512 yet!! 8O :lol: 

STFU stupid moronic noob troll!
October 4, 2006 10:01:01 PM

Quote:
if you ask me.


Have you *ever* been given even the slightest shadow of an impression that your opinion is cared for, wanted, or even (beggar the thought) asked for around here?

Quote:
Whats next 24mb of L2?


Hopefully, yes. In terms of computer specs, the term is generally "onward and upward", not "onward and downward".

Synergy6
October 4, 2006 10:20:43 PM

Originally Intel was saying that Yorkfield was their first 8 core processor due out in 2008.
October 4, 2006 10:25:18 PM

That link doesnt seem to have very good info, they are claiming that PNI = SSE4, but doesnt Core 2 already support SSE4, according to CPU-Z it does. And as already mentioned Yorkfield's supposed to be a unified cache / native quad core processor.
October 4, 2006 10:26:08 PM

MrsBytch is getting owned!...entretaining, now i resume my random things and let you people arguw(btw post more links)
October 4, 2006 10:28:31 PM

Quote:
That link doesnt seem to have very good info, they are claiming that PNI = SSE4, but doesnt Core 2 already support SSE4, according to CPU-Z it does. And as already mentioned Yorkfield's supposed to be a unified cache / native quad core processor.


PNI seems to be 40 additional SSE4 instructions. But yeah, there seems to be a good deal of contradictory information going around.
October 4, 2006 10:45:16 PM

Quote:
That link doesnt seem to have very good info, they are claiming that PNI = SSE4, but doesnt Core 2 already support SSE4, according to CPU-Z it does. And as already mentioned Yorkfield's supposed to be a unified cache / native quad core processor.


Core 2's new SSE instructions are now called Supplemental SSE3.
October 5, 2006 1:20:59 AM

Quote:
Intel probably would love to use Hyper transport 3.0 but they probably will never get to because of liscensing. That is why Intel is working on something of their own. Can not remember exactly what it is called right now though. Dues to the parternships for hypertransport, AMD has a loophole that keeps them out of antitrust trouble and at the same time keeps intel from using a technology AMD had a big hand in creating.


Actually, Intel might get it both ways (sort of): CSI (as labbby mentioned) and... HT 3.0 (though not ccHT), because Apple is a HyperTransport Consortium member. :wink:
(http://www.hypertransport.org/consortium/cons_members.cfm)


Cheers!
October 5, 2006 1:30:45 AM

Quote:
Cache is actually _less_ expensive than random logic. A large cache can be made redundant and will improve yields of a chip and lower prices.

A 12MB cache on 45nm is actually 33% smaller than the 8MB cache on 65nm in Kentsfield. So in relation to Kentsfield, the cache is smaller ;) 

Intel's chips benefit from such a cache because of the FSB interface. They're a bit farther away from memory. They compensate with the large cache and specialized stream prefetchers.

EDIT: changed 50% to 33% ;) 


Not only less expensive than logic; cache, in general, has a lower transistor density and produces less heat, comparatively.
Also interesting, is the use of such large L2 caches without recurring to L3 (for the time being); amazing how Intel's process is so efficient to allow 12MB L2 on-die!


Cheers!
October 5, 2006 1:31:39 AM

Quote:
Core 2's new SSE instructions are now called Supplemental SSE3.


Link, please?


Cheers!
October 5, 2006 1:37:43 AM

Quote:

Also interesting, is the use of such large L2 caches without recurring to L3 (for the time being)!


It seems to be that it's a 12MB L2 cache because it's just two Penryn die in the same package, much like Kentsfield. However, there are other reports that it is a one die quad-core.

My understanding, is that Nehalem would be the first one-die quad core from Intel. Nehalem will most definately have an nice large L3 cache shared between the four cores.
October 5, 2006 2:08:44 AM

Quote:
It seems to be that it's a 12MB L2 cache because it's just two Penryn die in the same package, much like Kentsfield. However, there are other reports that it is a one die quad-core.

My understanding, is that Nehalem would be the first one-die quad core from Intel. Nehalem will most definately have an nice large L3 cache shared between the four cores.


According to the referenced site, vr-zone, Yorkfield will be two Penryn w/ 6MB L2 each... on-die! :wink:

Let's wait & see what Altair can do with hyperfast links to >100 fold slower RAM & so scarce cache... on 65nm. At a mere [expected] 2.9GHz, one-die QC, it must be something truly outstanding, in order to be competitive with Yorkfield. For AMD's sake, it'd better be.


Cheers!
October 5, 2006 2:34:33 AM

2.9 GHZ is a tad disappointing. By that time, Conroe will hit 3.4-3.6 GHZ. AMD will have a hard time catching up. Odds don't look too good.
October 5, 2006 2:44:09 AM

There simply is not enough facts to speculate with any degree of certainty, but that has never stopped us before... :) 

K8L is represented in HKPEC as being 40% faster clock for clock. Let's take this 100% at face value (we simple have no way to judge how accurate this is, but so what?)

Right now a Conroe chip is +/- 25% faster clock for clock than a K8, so our new k8ls will be 1.4/1.25m => +/- 1.12 times faster than a Conroe clock for clock.

This wouldmak e a 2.9 ghz K8L chip equal to a 2.9 * 1.12 =>
3.2 to 3.3 ghz Conroe.

This is a good bit faster than the 2.67 Kenstfield speed expected this fall, the question is how far past 3.3 ghz can Intel push Kentfield (next generation) when it gets to 45 nanos?

If Intel can somehow get it's chips to 3.3 ghz+, they likely keep the crown, if not, AMD may retake.

If AMD gets well past 3 ghz, HT versus FSB may more and more start to help AMD.

But as I said, we just don't have anywhere near enough actual facts.
October 5, 2006 3:21:01 AM

Quote:
2.9 GHZ is a tad disappointing. By that time, Conroe will hit 3.4-3.6 GHZ. AMD will have a hard time catching up. Odds don't look too good.


Yep, it's even mentioned that Yorkfield will probably hit 3.73GHz@45nm. But, what's more, is that Penryn (hence, also Yorkfield) is another shift in Intel's microarchitecture; so, when vr-zone states that:
Quote:
It is hard to predict which architecture will win eventually but it seems like AMD has packed more innovations into their K8L architecture while Intel moving onto 45nm process benefits its Yorkfield greatly in terms of lower power consumption, higher clock speed and a much bigger L2 cache

it might be a bit misleading on what concerns Yorkfield, since we hardly know about the innards of such a new microarchitecture; it certainly will not be confined to "lower power consumption", higher clock speeds and a much bigger L2 cache".

Actually, less is even known about Altair, other than its inferior process technology (seems that the new SOI3 gen w/ two stressors doesn't cut it...), giving a (theoretical) top 2.9GHz stock (TDP?) and a non-mature 65nm node, according to the road(mixed)maps.

I'm very curious though, on how well Altair will perform with such "minute" cache; that, might be a true surprise.


Cheers!
October 5, 2006 4:20:08 AM

Quote:
There simply is not enough facts to speculate with any degree of certainty, but that has never stopped us before... :) 

K8L is represented in HKPEC as being 40% faster clock for clock. Let's take this 100% at face value (we simple have no way to judge how accurate this is, but so what?)

Right now a Conroe chip is +/- 25% faster clock for clock than a K8, so our new k8ls will be 1.4/1.25m => +/- 1.12 times faster than a Conroe clock for clock.

This wouldmak e a 2.9 ghz K8L chip equal to a 2.9 * 1.12 =>
3.2 to 3.3 ghz Conroe.

This is a good bit faster than the 2.67 Kenstfield speed expected this fall, the question is how far past 3.3 ghz can Intel push Kentfield (next generation) when it gets to 45 nanos?

If Intel can somehow get it's chips to 3.3 ghz+, they likely keep the crown, if not, AMD may retake.

If AMD gets well past 3 ghz, HT versus FSB may more and more start to help AMD.

But as I said, we just don't have anywhere near enough actual facts.


another speculative fanboyism...

nothing but barking...

how much did AMD paid u for this?

u are not helping the forum.
October 5, 2006 8:31:28 PM

However, all this is distant future; many things will happen before Q3 2007. This week noticed some massivization of X2 3600+ availability @ about $125-130. They put a nice shot on the Pentium Ds here but Price/Performance is all C2D $180 and above. We'll see what happens for christmas.
AMD will try the higher end of the curve while next year, Intel introduces new value chips to end the Sempron/Athlon64 domination there.
October 5, 2006 9:08:33 PM

What is annoying me at the moment is Intels virtual monopoly on Core chipsers = ridiculously high (chipset and hence) mobo prices. This is only going to get worse as AMD-ATI and nVidia-Intel integration progresses.

:evil:  to high mobo prices
October 5, 2006 9:16:51 PM

Agree, and VIA or SiS won't help for sure.
October 5, 2006 9:29:57 PM

Quote:
What is annoying me at the moment is Intels virtual monopoly on Core chipsers = ridiculously high (chipset and hence) mobo prices. This is only going to get worse as AMD-ATI and nVidia-Intel integration progresses.

:evil:  to high mobo prices


The most interesting thing about 965/946 Core2 mobos is that those from Intel itself are in fact quite cheap (100-150$). The only problem is they AFAIK lack overclocking options...
October 5, 2006 11:29:05 PM

Quote:
AMD is trying to put in embedded SiGe, and I recall that Intel's first public disclosure indicated this was a tough process.

http://www.stanford.edu/class/ee311/NOTES/Intel%20Strai...

See figure 12 to see defects on a wafer for the SiGe process. It tooks some some work it appears. I would not be surprised if AMD is re-inventing the wheel here.

This is a good paper to read to get an idea of Intel's 90 nm process.


Yes, I did had a look at that paper, sometime ago; even with third gen sSOI (IBM, of course), things don't look that 'fantastic', although, from a pure technological point of view, amazing strides have/are being made with current techniques, namely, strained silicon.
I've also found this very interesting article on AMD/IBM 3rd-gen SOI, where it's stated that:

Quote:
Since electrons move faster through silicon with a (100) orientation and holes move faster through silicon with a (110) orientation (the orientation of most substrates), hybrid orientation technology (HOT) has developed to increase drive current as well. This approach, so far pursued mainly by IBM (East Fishkill, N.Y.), has resulted in 20% reduction in gate delays on bulk silicon.2,3 Though this process may be limited by complexity and cost, engineers are working on simplifying the process and making it more manufacturable.


Curiously, they [IBM] don't seem to use entire wafer strained silicon with HOT; now, if I understand correctly, stressors & strained silicon are applied on a per-transistor basis, in SOI technology (since there are several stressing steps to be applied); if true, that would certainly be a major handicap vs Intel process... or, I'm reading it wrong?

(http://www.reed-electronics.com/semiconductor/index.asp?layout=articlePrint&articleID=CA6294195)

Edit: Ooops! Wrong link!


Cheers!
October 5, 2006 11:45:28 PM

Quote:
That Intel feels they need 12mb of L2 on their quad 45nm to compete with AMD's quad 65nm part says a lot.
Its actually ridiculous if you ask me. Whats next 24mb of L2? I havent even gotten to 512 yet!! 8O :lol: 


That AMD fanboys feel they need to somehow twist every detail of Intel’s architecture to make AMD look competitive says a lot
It’s actually ridiculous if you ask me. What’s next, protests outside of Intel’s dozen some odd FABs? AMD doesn’t even have 3 fully functional fabs yet!! 8O :lol: 
October 7, 2006 3:57:29 AM

/bump
October 7, 2006 2:26:50 PM

Quote:

In a better world, AMD would have more Fab space and Intel would use on-die memory controller with Hyper Transport 3.0. It's only that neither does for now... but all will eventually, so stop whining :twisted: .

As for me, I'll use any CPU that deliver on the performances front at the price I'm ready to pay. You should do the same!!! :idea:


Intel probably would love to use Hyper transport 3.0 but they probably will never get to because of liscensing. That is why Intel is working on something of their own. Can not remember exactly what it is called right now though. Dues to the parternships for hypertransport, AMD has a loophole that keeps them out of antitrust trouble and at the same time keeps intel from using a technology AMD had a big hand in creating.

Liscensing is not a problem. Hypertransport is an open standard. Also, AMD and Intel have agreament (wrong spelling? sorry if that's the case) that permit them to use each other technology. The problem reside in implementing their own CSI (Intel HyperTransport equivalent) after using HTr. System designer and everybody that would build/own Intel system on HyperTransport would be unwilling (at least, not to say pissed off) to switch to Intel new system on CSI. That is the real reason behind Intel not using HT right now, at least that what I think.

For me, if CSI is really better than HT3.0 and is easier to "upgrade" to faster interconnexions, than all is good. But if it just equal HT3.0, than I think it a waste of time for both Intel and us. Only time will tell tough.
October 7, 2006 2:33:20 PM

Quote:
Intel probably would love to use Hyper transport 3.0 but they probably will never get to because of liscensing. That is why Intel is working on something of their own. Can not remember exactly what it is called right now though. Dues to the parternships for hypertransport, AMD has a loophole that keeps them out of antitrust trouble and at the same time keeps intel from using a technology AMD had a big hand in creating.


Actually, Intel might get it both ways (sort of): CSI (as labbby mentioned) and... HT 3.0 (though not ccHT), because Apple is a HyperTransport Consortium member. :wink:
(http://www.hypertransport.org/consortium/cons_members.cfm)


Cheers!

Cool!

Does that open the door for new core design especially for Apple and than the one for "regular" PC.

Still, like I said before, I REALLY HOPE CSI will deliver on the performances front, or Intel will have lost both my and your time by retarding the performances gain possible by using HT now for on-die memory controler CPU. :evil: 

But if it does, I just can't wait!!! That and upcoming K8L :wink:
October 7, 2006 2:44:28 PM

Quote:
What is annoying me at the moment is Intels virtual monopoly on Core chipsers = ridiculously high (chipset and hence) mobo prices. This is only going to get worse as AMD-ATI and nVidia-Intel integration progresses.

:evil:  to high mobo prices


I just hope your wrong, but I doubt it.. :?

On the other way around, it'll give more tool to both AMD and Intel to adjust their price to stay competitive on the price/performances front. If, say in 2 years, AMD come out with a super CPU that crush the upcoming NEHALEM, than Intel will have the opportunity to lower both their CPU and chipset price to stay competitive. And it'll be the same for AMD.

So, longer term, it might be better for both company to have control of both cpu and chipset manufacturing.

Also, it might open a door for SiS and VIA to come back in that area. It wouldn't be too soon for any of these 2 company I say :twisted:
October 7, 2006 7:03:10 PM

Quote:
Actually, Intel might get it both ways (sort of): CSI (as labbby mentioned) and... HT 3.0 (though not ccHT), because Apple is a HyperTransport Consortium member. :wink:
(http://www.hypertransport.org/consortium/cons_members.cfm)


Quote:
Cool!

Does that open the door for new core design especially for Apple and than the one for "regular" PC.


(nVidia is also a HTX member.).

No, I didn't mean what you interpreted; I just meant Apple MBs might have access to both protocols (HT & PCIe) without going directly through Intel; despite the highly speculative character of this eventuality, I guess Intel wouldn't mind... neither the consortium. My opinion.


Cheers!
!