Intel Yorkfield Vs. AMD Altair (K8L)

[Retardicus]

Found some interesting information on Yorkfield. Yorkfield is a quad core composed of two 45nm Penryn die. Apparently it's out in Q3 2007.

http://www.vr-zone.com/?i=4109

 

[lcdguy]

lol, true. Imagine an amd chip that could effciently use 12mb of cache what would intel do then

 

[theaxemaster]

Hmm...intel seems to be upping the clock and adding cache again, sound familiar?

It is hardly a "vs." article, its just a few details on intel's upcoming chip, and a scant mention of AMD at the end. Very misleading title.

 

[crazypyro]

Very misleading title.

misleading, yes
but hey isn't half of journalism about drawing in readers

 

[jaguarskx]

Hmm... 12MB of cache....

While great for databases, I doubt the typical user would benefit from even having 6MB of cache. I think there were even two conflicting articles about the benefits between 2MB and 4MB of cache.

 

[salvador]

Found some interesting information on Yorkfield. Yorkfield is a quad core composed of two 45nm Penryn die. Apparently it's out in Q3 2007.

http://www.vr-zone.com/?i=4109

Actually, I believe that vr-zone is mistaken about Yorkfield.

Conroe is a Native Dual-Core on 65nm with 4mb SHARED L2.
Kenstfield is the "glued" quad-core (same as Pentium D) part on 65nm, with two Conroe dies on the same PCB, and two L2 caches..

Yorkfield will be the Native Quad-Core part, on 45nm with a 12mb SHARED L2.

linky:
http://digitimes.com/bits_chips/a20060928A2007.html
http://www.theregister.co.uk/2005/12/05/intel_45nm_roadmap/

 

[Guest]

Who cares about the amount of cache on a processor, 12 meg says a lot about the Core 2 architechture, thats is: lot's of cache with smart logic can negate the effects of the aging FSB interconnect... Also why put this much? cause they can! and it's good for marketing!

Amd could'nt make good use of that much cache because they went another road with their design. The ODMC is more elegant I agree but as long as you get results( performance/price ,performance /whatt, etc) who care how it's done!

Amd did'nt go down that path because they dont have the technology Intel has to cram that much Cache, that might change with Z-Ram and then who knows, maybe they will have 64meg of L2 but then again they might be fine with 1 meg...

 

[NightlySputnik]

That Intel feels they need 12mb of L2 on their quad 45nm to compete with AMD's quad 65nm part says a lot.
Its actually ridiculous if you ask me. Whats next 24mb of L2? I havent even gotten to 512 yet!! 8O :lol:

Let me think... Got it: FANBOY AT WORK!!!

What do you care about Intel adding more cache to their cpu as long as it deliver on performances front???? Cache just happen to be one of Intel strengh (as oppose to AMD who's latency generally get's worst than Intel when bigger), so why not use it. These guys ask themself if more cache will bring the performances gain worth the extra die space. If so they use it. Plain and simple!

AMD, on the other hand, is way more "Fab limited", so they can't afford to play that game. And I get their point too, that's how they survive and managed to gain 20-30% of overall x86 cpu shipment.

In a better world, AMD would have more Fab space and Intel would use on-die memory controller with Hyper Transport 3.0. It's only that neither does for now... but all will eventually, so stop whining :twisted: .

As for me, I'll use any CPU that deliver on the performances front at the price I'm ready to pay. You should do the same!!! :idea:

 

[Guest]

Itanium 2 Montecito has 24 meg, must be marketing....

 

[Guest]

They're working on Common System Interface(CSI).

HT is actually open and not proprietary to AMD
Wiki will tell you that!

Only thing to that is proprietary to AMD is HTc (with cache coherency) used to interconnect CPU's.

(thanks to whoever posted that a while ago can't remember )

 

[Retardicus]

All I can say is all that cache is gonna cost money. Hope it's worth the price.

Cache is actually _less_ expensive than random logic. A large cache can be made redundant and will improve yields of a chip and lower prices.

A 12MB cache on 45nm is actually 33% smaller than the 8MB cache on 65nm in Kentsfield. So in relation to Kentsfield, the cache is smaller

Intel's chips benefit from such a cache because of the FSB interface. They're a bit farther away from memory. They compensate with the large cache and specialized stream prefetchers.

EDIT: changed 50% to 33%

 

[gOJDO]

That Intel feels they need 12mb of L2 on their quad 45nm to compete with AMD's quad 65nm part says a lot.
Its actually ridiculous if you ask me. Whats next 24mb of L2? I havent even gotten to 512 yet!! 8O :lol:

STFU stupid moronic noob troll!

 

[Synergy6]

if you ask me.

Have you *ever* been given even the slightest shadow of an impression that your opinion is cared for, wanted, or even (beggar the thought) asked for around here?

Whats next 24mb of L2?

Hopefully, yes. In terms of computer specs, the term is generally "onward and upward", not "onward and downward".

Synergy6

 

[Heyyou27]

Originally Intel was saying that Yorkfield was their first 8 core processor due out in 2008.

 

[Corasik]

That link doesnt seem to have very good info, they are claiming that PNI = SSE4, but doesnt Core 2 already support SSE4, according to CPU-Z it does. And as already mentioned Yorkfield's supposed to be a unified cache / native quad core processor.

 

[mandraque]

MrsBytch is getting owned!...entretaining, now i resume my random things and let you people arguw(btw post more links)

 

[Retardicus]

That link doesnt seem to have very good info, they are claiming that PNI = SSE4, but doesnt Core 2 already support SSE4, according to CPU-Z it does. And as already mentioned Yorkfield's supposed to be a unified cache / native quad core processor.

PNI seems to be 40 additional SSE4 instructions. But yeah, there seems to be a good deal of contradictory information going around.

 

[accord99]

That link doesnt seem to have very good info, they are claiming that PNI = SSE4, but doesnt Core 2 already support SSE4, according to CPU-Z it does. And as already mentioned Yorkfield's supposed to be a unified cache / native quad core processor.

Core 2's new SSE instructions are now called Supplemental SSE3.

 

[joset]

Intel probably would love to use Hyper transport 3.0 but they probably will never get to because of liscensing. That is why Intel is working on something of their own. Can not remember exactly what it is called right now though. Dues to the parternships for hypertransport, AMD has a loophole that keeps them out of antitrust trouble and at the same time keeps intel from using a technology AMD had a big hand in creating.

Actually, Intel might get it both ways (sort of): CSI (as labbby mentioned) and... HT 3.0 (though not ccHT), because Apple is a HyperTransport Consortium member.
(http://www.hypertransport.org/consortium/cons_members.cfm)


Cheers!

 

[joset]

Cache is actually _less_ expensive than random logic. A large cache can be made redundant and will improve yields of a chip and lower prices.

A 12MB cache on 45nm is actually 33% smaller than the 8MB cache on 65nm in Kentsfield. So in relation to Kentsfield, the cache is smaller

Intel's chips benefit from such a cache because of the FSB interface. They're a bit farther away from memory. They compensate with the large cache and specialized stream prefetchers.

EDIT: changed 50% to 33%

Not only less expensive than logic; cache, in general, has a lower transistor density and produces less heat, comparatively.
Also interesting, is the use of such large L2 caches without recurring to L3 (for the time being); amazing how Intel's process is so efficient to allow 12MB L2 on-die!


Cheers!

 

[joset]

Core 2's new SSE instructions are now called Supplemental SSE3.

Link, please?


Cheers!

 

[Retardicus]

Also interesting, is the use of such large L2 caches without recurring to L3 (for the time being)!

It seems to be that it's a 12MB L2 cache because it's just two Penryn die in the same package, much like Kentsfield. However, there are other reports that it is a one die quad-core.

My understanding, is that Nehalem would be the first one-die quad core from Intel. Nehalem will most definately have an nice large L3 cache shared between the four cores.

 

[joset]

It seems to be that it's a 12MB L2 cache because it's just two Penryn die in the same package, much like Kentsfield. However, there are other reports that it is a one die quad-core.

My understanding, is that Nehalem would be the first one-die quad core from Intel. Nehalem will most definately have an nice large L3 cache shared between the four cores.

According to the referenced site, vr-zone, Yorkfield will be two Penryn w/ 6MB L2 each... on-die!

Let's wait & see what Altair can do with hyperfast links to >100 fold slower RAM & so scarce cache... on 65nm. At a mere [expected] 2.9GHz, one-die QC, it must be something truly outstanding, in order to be competitive with Yorkfield. For AMD's sake, it'd better be.


Cheers!

 

[accord99]

Core 2's new SSE instructions are now called Supplemental SSE3.

Link, please?


Cheers!

http://en.wikipedia.org/wiki/SSSE3

 

[wickedmonster]

2.9 GHZ is a tad disappointing. By that time, Conroe will hit 3.4-3.6 GHZ. AMD will have a hard time catching up. Odds don't look too good.