Native 2MB L2 Cache Conroe

[Parrot]

Intel are to produce native 2MB L2 cache Conroes in 2007.
LINK

 

[shadowed]

Would these then require a shared L3 cache ?

 

[shadowed]

Thanks JJ, that article had me confused.... not hard to do though :?

 

[qcmadness]

Would these then require a shared L3 cache ?

No, E6300, E6400 are 2 Meg L2 shared cache.

I am searching for confirmation that this article is not correct, I thought Allendale had already taped out and that makes up the E6300/E6400 CPUs.

I think this report is inacurrate.

I think the article is about the native 2MB cache die.
Allendale are produced using Conroe masks with 2MB cache disabled.

By using Allendale masks, Intel can then lower the costs of E6300 and E6400.
I think the major reason is for the more price pressure to AMD.

 

[NMDante]

Would these then require a shared L3 cache ?

No, E6300, E6400 are 2 Meg L2 shared cache.

I am searching for confirmation that this article is not correct, I thought Allendale had already taped out and that makes up the E6300/E6400 CPUs.

I think this report is inacurrate.

I think it's more that Intel will make a 2M cache and not a disabled 4M cache version.

At least, that's the way I understood the article.

Although they have 2MB L2 and 4MB L2 versions, the 2MB one is made by only disabling half of the L2 Cache.

So, maybe to reduce cost of the low end C2Ds, they will make a native 2M cache for them, from now on.

**edit**
dang, qcmadness beat me... blah! LOL

 

[evilr00t]

That explains why Intel doesn't particularly want to release the E4300 now.

 

[ltcommander_data]

I previously talked about this here:

http://forumz.tomshardware.com/hardware/Intel-Core-uArch-coming-MPftopic-205600-days0-orderasc-25.html

So I'll just copy my comments over again:

The current E6300 and E6400 are actually disabled Conroe parts which explains why availability was fairly slow during launch and probably contributed lower Q3 results than would otherwise be possible. This has actually been pointed out before:

You'll find plenty of sources that will tell you the code name for these 2MB Core 2 Duo processors is "Allendale," but Intel says otherwise. These CPUs are still code-named "Conroe," which makes sense since they're the same physical chips with half of their L2 cache disabled. Intel may well be cooking up a chip code-named Allendale with 2MB of L2 cache natively, but this is not that chip.

http://techreport.com/reviews/2006q3/e6300-vs-sff/index.x?pg=1

It's just that CPU-Z mislabels them which propagates the confusion. I'm guessing going to a true 2MB core with the smaller die sizes will allow price cuts which makes sense since it's likely the 2.93GHz E6800 in January will fall into the curret E6700's price point causing a price cascade.

 

[qcmadness]

That explains why Intel doesn't particularly want to release the E4300 now.

A lower cost is always favourable for manufacturers

 

[qcmadness]

I previously talked about this here:

http://forumz.tomshardware.com/hardware/Intel-Core-uArch-coming-MPftopic-205600-days0-orderasc-25.html

So I'll just copy my comments over again:

The current E6300 and E6400 are actually disabled Conroe parts which explains why availability was fairly slow during launch and probably contributed lower Q3 results than would otherwise be possible.

I don't see this as the reason.
Intel can tune the product mix from E6600 to E6400 / E6300.
Just the same as AMD.

 

[Slobogob]

I thought the 3040 and 3050 Xeon had 4MB L2? At least that´s what newegg said and i believe the intel specs did mention that too. What´s right and what´s wrong?

 

[ltcommander_data]

I don't see this as the reason.
Intel can tune the product mix from E6600 to E6400 / E6300.
Just the same as AMD.

That doesn't make sense. If the E6300 and E6400 are actually full 4MB Conroe dies, Intel can tune the mix all the want to optimize yields for the lower clock speeds, but the resulting dies are still larger than the need to be since you only need half the cache. So they are still not making as much as they could be with a 2MB L2 native die. Right now using full 4MB dies for the E6300 and E6400 is fine since the large size of the Conroe die means they probably have a lot of defective parts that they would otherwise have to through away. But, as the yields improve there are less defective Conroe parts that can have half their cache economically disabled which is why Intel is transferring to a true 2MB Allendale.

 

[ltcommander_data]

I thought the 3040 and 3050 Xeon had 4MB L2? At least that´s what newegg said and i believe the intel specs did mention that too. What´s right and what´s wrong?

The Xeon 3000 series use Conroe cores and they correspond exactly to Core 2 Duos. Both the 3040 and 3050 have 2MB L2 caches just like the E6300 and E6400. It's only in the Xeon 5100 Woodcrests that even the lower end 1067MHz FSB parts still have 4MB L2 caches.

 

[1Tanker]

I don't see this as the reason.
Intel can tune the product mix from E6600 to E6400 / E6300.
Just the same as AMD.

That doesn't make sense. If the E6300 and E6400 are actually full 4MB Conroe dies, Intel can tune the mix all the want to optimize yields for the lower clock speeds, but the resulting dies are still larger than the need to be since you only need half the cache. So they are still not making as much as they could be with a 2MB L2 native die. Right now using full 4MB dies for the E6300 and E6400 is fine since the large size of the Conroe die means they probably have a lot of defective parts that they would otherwise have to through away. But, as the yields improve there are less defective Conroe parts that can have half their cache economically disabled which is why Intel is transferring to a true 2MB Allendale.Yeah, this makes sense. Makes me wonder though, if they create a specific Allendale wafer, will everything else(except cache amount)be the same and if not.....will this hurt Allendales awesome overclocking abilities? I guess this is where they are expecting the E4300's to come from....E6300/E6400's not making the grade. If that's the case, the E4300 might not be the stellar overclocker that everyone is anticipating.

 

[ltcommander_data]

Well the E6300 and E6400 being cache disabled Conroes I suppose the extra cache acting as a heatsink may help in overclocking. Still I don't think going to native 2MB dies is a bad thing since even full 4MB Conroes overclock very well.

In the case of the E4300 it should be just like the 805D. Since the E4300 are made from parts that can't get to 1067MHz FSB you're likely to see parts that perhaps get up to a 1000MHz FSB reliably from a 800MHz FSB. That is plenty of overclocking for a locked multiplier. Just like how many 805Ds could get very close if not at 800MHz FSBs from their 533MHz base.