DDR3 has a better Bandwitdh per watt. Comparing to DDR2-800, DDR3-800/1067/1333 use only 72%, 83%, and 95% of power. DDR3 is more power saving at the same time it enhanced the bandwidth.
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Taking DDR3-1066 (7-7-7), DDR3-1333 (8-8-8), and DDR3-1600 (9-9-9) as examples, we need to count the clock speed in order to calculate the CAS Latency, and the results are 13.125ns, 12ns, and 11.25ns. They get 25% faster.
According to a report concerning DDR3 Volume & Pricing Forecast relative to DDR2 from iSuppli, DDR3 would only share 10% of the market in 2007 where its price is 50%higher than DDR2. In 2008, it’s better. DDR3 would rise to 25% of the market share and its price would drop to a similar price of DDR2. Finally, DDR3 is expected to be the main technology in 2009.
You could say the same about PCIe 2.0 since the PCIe bus isn't even being used to its full capacity right now, but yeah, I'll agree that it's still a long way off from becoming mainstream.
Did you guys notice the ULTRA High latenceys... Seems like with every step forward, they take a step back . . .
Why don't you read the whole article before you make a wrong conclusion?
The real time latency will be reduced compared to DDR2.
Pay attention on this part:
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Regarding with the CAS Latency, Kim Gyou Joong, Senior Engineer, Samsung Electronics Corporation, said all of the DDR2-533 (CL 4-4-4), DDR2-667 (CL 5-5-5) and DDR2-800 (CL6-6-6) have 15ns latency according to JEDEC. CAS Latency (CL) is the time (in number of clock cycles) that elapses after the memory controller sends a request to read a memory location and before the data is sent to the module's output pins. As CAS Latency only specifies the delay between the request and the first bit, the clock speed specifies the latency between bits. Thus, when reading bursts of data, a higher clock speed can be faster in practice, even with a worse CAS Latency.
Taking DDR3-1066 (7-7-7), DDR3-1333 (8-8-8), and DDR3-1600 (9-9-9) as examples, we need to count the clock speed in order to calculate the CAS Latency, and the results are 13.125ns, 12ns, and 11.25ns. They get 25% faster. So we should bear in mind that CAS Latency is not related to CL only, but also the clock speed.
Very nice indeed.But I guess price does play a role in most everyday purchases,so ya,how much will it cost???Any ideals???TY for posting this info anyways.Nice to see what's up and coming.Goodluck.
Dahak
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One, check who you reply to.
Two, its as valid information as posting AMD's market share
Three, sod off.
Check who I reply to???
I assumed maybe you were smart enough to know that since you didnt say the quote, you would know I wasnt talking to you!!?? My appologies, I was wrongabout that.
Telling people DDR3 is faster than DDR2 is going to affect market share??
If anyone didnt already know that, they need a head check.
Apparently you are not smart enough to read the sod off notice.
By the way using "????" "!!!!" qualifies at 1337, so be ready for the flames appropriate to such actions.
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Telling people DDR3 is faster than DDR2 is going to affect market share??
If anyone didnt already know that, they need a head check.
And you hordesters posting things such as, "AMD not to backdown" is any more worthy of being in this section?
Once again, sod off.
Aaah yes, but as the DDR2 process matures, we're getting 1Ghz DDR2 with CL 5-5-5 timings instead of 800Mhz DDR2 with CL 6-6-6 timings. And that's not even counting the newest Corsair Dominator series @ 1.1Ghz and ridiculous CL 4-4-4 timings.
So the problem with latencies is that the mature, older process will probably always beat the newest process. It was that way with DDR1 -> DDR2 and this seems to be repeating itself.
It's funny that integrating the memory controllers directly opposes the problem that DDRx transitions cause. IMCs reduce latencies, while DDRx transitions aren't good for overall latencies...
Aaah yes, but as the DDR2 process matures, we're getting 1Ghz DDR2 with CL 5-5-5 timings instead of 800Mhz DDR2 with CL 6-6-6 timings. And that's not even counting the newest Corsair Dominator series @ 1.1Ghz and ridiculous CL 4-4-4 timings.
So the problem with latencies is that the mature, older process will probably always beat the newest process. It was that way with DDR1 -> DDR2 and this seems to be repeating itself.
It's funny that integrating the memory controllers directly opposes the problem that DDRx transitions cause. IMCs reduce latencies, while DDRx transitions aren't good for overall latencies...
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