2-core P-4 2.8GHz Prescott vs. 2-processor Xeon 2.4GHz?

The Pentium 4 630 isn't dual core. Its a single core with hyper threading.

Scrap both those ideas in my opinion...

The Pentium 4 630 isn't dual core. Its a single core with hyper threading.

So, the question now is: - what is better:
a P-4 3.0GHz Prescott w/ hyper threading
or
an old dual-processor Xeon 2.4GHz?

What difference do make:
the MMX,SSE, SSE2, SSE3, and EM64T (in newer P-4 Prescott)
vs.
MMX, SSE, SSE2 (in older Xeon Prestonia) ?

(Extended Memory 64 Technology) A 64-bit upgrade to Intel's 32-bit x86 (IA-32) architecture. EM64T adds a set of 64-bit instructions that are compatible with AMD's 64-bit instructions (see AMD64). Introduced in 2004, Xeons (code named Nocoma) were the first CPUs to incorporate EM64T along with other enhancements such as the PCI Express bus and DDR2 memory.

With the introduction of EM64T, Intel offers 64 bits in two CPU families: the 32/64-bit x86 (IA-32) line and the 64-bit Itanium (IA-64) line.

SSE3 Instructions Set

Another innovation in the Prescott core is the introduction of the new SIMD instructions set, which was first known as PNI (Prescott New Instructions), but then got a new marketing name – SSE3. In fact, I do not think it would be fair to call the SSE3 instructions set fully-fledged. SSE3 includes only 13 new instructions, which doesn’t look serious enough, especially against the background of the pervious SIMD instructions sets from Intel offering over a few dozens of new instructions. Moreover, SSE3 is not a new instructions set developed for some specific tasks. It is none other but a few additional isolated instructions, which kind of “correct a few bugs” in the already existing sets.

SSE3 includes the following new instructions:

* HADDPS, HSUBPS, HADDPD, HSUBPD. These are horizontal operations with SSE2 registers, which have been forgotten during SSE2 development, for some reason. These commands can be extremely helpful for 3D graphics processing, since they allow simplifying the subtraction of such a widely spread value as scalar vector product.
* ADDSUBPS, ADDSUBPD, MOVSHDUP, MOVSLDUP, MOVDDUP. These instructions are intended for work with complex numbers. These commands can be helpful for undulatory processes calculation and work with sound, i.e. where fast discrete Fourier transformation is applied.
* FISTTP. This is anew instruction for the arithmetic co-processor, which allows transforming the co-processor stack into an integer type. For some unknown reasons, this operation was absent in x87 instructions set.
* LDDQU. This instruction serves for unaligned data loading. It can be helpful for video compression tasks.
* MONITOR, MWAIT. These instructions serve to optimize multi-threaded applications. They will allow achieving better performance results in systems with enabled Hyper-Threading technology and avoid threads blocking, just as we have just described above.

Although Intel released the SSE3 instructions guidelines for software developers last summer, there are no programs yet, where the new instructions could really be used. However, we know for sure that they are to come very soon now. First of all, SSE3 instructions will be used in various video codecs, because according to Intel, LDDQU instruction could speed up video compression by 10% if used in data encoding algorithms. By the way, the new version of Intel C++ 8.0 compiler supports SSE3 instructions, which means that other software employing SSE3 is already on the way.