Cache Disabling...How?

[1Tanker]

This is a two-pronged question, that i'm not sure many will know the answer to.

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I've never seen any info on either of these questions, and i wonder if any of our resident process experts(possibly JJ, Joset, JkFlipFlop) or anyone else for that matter, knows the answer.

 

[Grimmy]

To be honest.

1.) I dunno

2.) I... dunno.

The question I have is.. to know that info, would you try to consider in re-activating the disabled cach?

 

[1Tanker]

To be honest.

1.) I dunno

2.) I... dunno.

The question I have is.. to know that info, would you try to consider in re-activating the disabled cach?

That would be cool if you could. Even if you could get an Allendale up to 3MB cache. I highly doubt it's feasable, or people would be doing it already, and Conroe sales would really suffer.

 

[dasickninja]

wouldn't that necessitate a clean room?

 

[1Tanker]

wouldn't that necessitate a clean room?

Probably.That wasn't the reason for my post anyways.... Just interested in the process.

 

[13thmonkey]

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I'd think that given that a fault can occur anywhere it could be a single gate that forms a bit, or it could be in an area that controls a a row or a column or a byte, and hence the fault could be any size.

The problem with re-enabling these is that you'd have to ensure that you knew precisley where the fault was and block it out so that it could not be used.

I wonder if the old days of unlocking multi's with a pencil might come back.

 

[1Tanker]

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I'd think that given that a fault can occur anywhere it could be a single gate that forms a bit, or it could be in an area that controls a a row or a column or a byte, and hence the fault could be any size.

The problem with re-enabling these is that you'd have to ensure that you knew precisley where the fault was and block it out so that it could not be used.

I wonder if the old days of unlocking multi's with a pencil might come back.Too bad it wasn't easy like unlocking PS/VS on a GPU with software like Rivatuner.

 

[shinigamiX]

Maybe they stuck a small pin through the die - just like my friend did with his flatmate's box of condoms 8O

 

[Johanthegnarler]

That's no good. 8O

..and i'll follow that up with a.. oh jeezuz.

 

[turpit]

This is a two-pronged question, that i'm not sure many will know the answer to.

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I've never seen any info on either of these questions, and i wonder if any of our resident process experts(possibly JJ, Joset, JkFlipFlop) or anyone else for that matter, knows the answer.

I seem to recall Jack discussing this a in thread not to long ago.

If I recall correctly, the chip has an internal "fuse". If the cache bank is defective, they overvolt that circuit and pop the fuse, permenantly locking of that cache.

I also recall they mentioned excess cache to compensate for bad cache.

Im sure JJ will be by with an accurate answer for ya soon enough

 

[1Tanker]

This is a two-pronged question, that i'm not sure many will know the answer to.

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I've never seen any info on either of these questions, and i wonder if any of our resident process experts(possibly JJ, Joset, JkFlipFlop) or anyone else for that matter, knows the answer.

I seem to recall Jack discussing this a in thread not to long ago.

If I recall correctly, the chip has an internal "fuse". If the cache bank is defective, they overvolt that circuit and pop the fuse, permenantly locking of that cache.

I also recall they mentioned excess cache to compensate for bad cache.

Im sure JJ will be by with an accurate answer for ya soon enoughThanks... I kind of figured that if Jack knew how it was done, he would have explained it previously. I do seem to remember him mentioning something about redundancy WRT cache.

 

[joset]

Hi!

Very interesting questions... it's darn late, here (5.15 am); I'll return tomorrow.


Cheers!

 

[shinigamiX]

That's not late, that's early.

 

[1Tanker]

Disabling cache is done routinely, but I myself am uncertain how it is done, it cannot be done easily in packaging as the complexity of cache the logic to index bad cache I would suspect is very complicated.

I will research this and get back to you...

The 'blow out the fuse' explanation is used to set various pin states in packaging to set various processor characteristics - such as VID settings and such. I doubt this is how certain sections of cache are disabled.

Jack

I look forward to your post. I figured it would be an interesting, yet little-known subject. Maybe the manufacturers classify that info as trade secrets, and therefore don't publish it? :?

 

[Atolsammeek]

I dont think they touch the Intel chip itself. I think it something to do underneath the chip. I could be wrong. But it a idea.

Just to point out the chip to the right upside down look at the center or the left next to the dual core.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2866

 

[m25]

This is a two-pronged question, that i'm not sure many will know the answer to.

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

I've never seen any info on either of these questions, and i wonder if any of our resident process experts(possibly JJ, Joset, JkFlipFlop) or anyone else for that matter, knows the answer.

1-They take a hammer and a nail and BANG, hit the area of cache to eliminate...this was too easy.
2-(I am serious here) No wonder that defective areas are random in size but since they are groupped in packages, like MB RAM, I guess you can't disable just say 16K of it just like you can't take out a chip from a RAM slot and still have it work. Even if they could do so, the result would be an incredible spectrum of products with variable specs (cache size), that is a marketing nightmare.

 

[turpit]

Disabling cache is done routinely, but I myself am uncertain how it is done, it cannot be done easily in packaging as the complexity of cache the logic to index bad cache I would suspect is very complicated.

I will research this and get back to you...

The 'blow out the fuse' explanation is used to set various pin states in packaging to set various processor characteristics - such as VID settings and such. I doubt this is how certain sections of cache are disabled.

Jack

Ah, thank you for correcting the mis-information I fed Tanker

 

[MU_Engineer]

Well, #1 is actually not too hard to answer for most all lower-cache CPUs made. Intel (and AMD) simply use different mask sets for lower-cache and higher-cache units. So >95% of all Allendales are made with only 2MB L2 to begin with, as are AMD's 512KB L2 chips. This saves on die space and is more profitable for the makers as you get more chips per wafer. There also aren't nearly enough bad high-cache chips that go bad and have to be disabled. JKflipflop told me this is actually how it's done.

#2. I'd guess that cache gets crapped up in a region as a particle hits the die or something so it will be a random number.

 

[r0ck]

http://www.hkepc.com/bbs/itnews.php?tid=686996&starttime=0&endtime=0
Current E6300/E6400s have 2MB disabled though. They'll be making a 'native' 2MB Allendale in Feb07.

 

[MU_Engineer]

Well I'll be...I guess JK wasn't right after all. That does seem odd for Intel to disable the cache on those chips as the fail rate in the industry is about 5%. I know for a fact that AMD uses separate masks for the 512KB and 1MB L2 chips (it kind of has to.) So I guess Intel must have a problem getting all 4MB cache online (not likely,) they really busted their butts to get Conroe shot and out and thus only made 1 mask (more likely) or they only had one line open to make one die type of CPU and of course it was the full 4MB one (sort of likely, but less so that #2 because of the following.)

What this does say is that Intel has a ton of 65nm production capacity as it's willing to toss 4MB cache versions off as 2MB ones. I bet the guys in Sunnyvale are wishing that they had that luxury...

 

[joset]

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

Here's a simple & quick answer to both your questions (Intel's "I5" procedures for the Pentium Pro cache redundancy testing, 1993-1997); although this doesn't address, in depth, the DFT (Design For Testing) methods during process, nor the more sophisticated techniques (both Soft & Hard) available today, it provides a basic understanding of redundancy/yield and the Known Good Die factor (KGD), among others.
I don't have the time now, but I'll post some more info on wafer/die testing process, asap.

http://developer.intel.com/technology/itj/q41997/pdf/manufacturing.pdf

(Again, very interesting points; I've just missed those issues, while going through litho/manufacturing...)


Cheers!

 

[joset]

Maybe the manufacturers classify that info as trade secrets, and therefore don't publish it? :?

Not at all; there's plenty of info around (and very interesting stuff, indeed!)


Cheers!

 

[1Tanker]

1. How would Intel/AMD disable cache during manufacturing?

i.e. Say they have a Core2Duo chip that (at best) should have 4096KB's L2 cache. Let's say that 256K of that is non-functional, and therefore they disable a whole 2048KB's of cache, to end up with an Allendale(which they would obviously set to a lower multiplier...7x or 8x). How would they disable the cache(i'm assuming that cache is the same as Memory=Columns x Rows)?

2. This may be even harder to answer.

Say there is defective cache on the chip, would the defective "amounts" be random sizes.. i.e. 278KB, or would the defective areas be in amounts of say 64KB/128KB/256KB/512KB?

Here's a simple & quick answer to both your questions (Intel's "I5" procedures for the Pentium Pro cache redundancy testing, 1993-1997); although this doesn't address, in depth, the DFT (Design For Testing) methods during process, nor the more sophisticated techniques (both Soft & Hard) available today, it provides a basic understanding of redundancy/yield and the Known Good Die factor (KGD), among others.
I don't have the time now, but I'll post some more info on wafer/die testing process, asap.

http://developer.intel.com/technology/itj/q41997/pdf/manufacturing.pdf

(Again, very interesting points; I've just missed those issues, while going through litho/manufacturing...)


Cheers!Thanks Joset. Interesting, although i figured it would be pretty technical(my brain hurts now)..I'm positive i have ADD...especially when i was in high-school. What i get out of that article, is how they test for bad cache, and how they replace it with a redundant cell. It doesn't specifically(that i can see) tell how they would disable cache... i.e. with a C2D chip, and lets say there's ~256KB defective....they would then disable 2048KB leaving 2048 KB working cache for an Allendale. It doesn't really say how they disabled it...unless the flash cell disables it by sending high voltage into it?

For example, as per article:

a sub-array is replaced by it's neighbouring sub-array, closest to the redundant sub-array. The sub-arrays between the bad sub-array and the redundant sub-array are also switched to their neighbouring sub-array. All this switching is done by muxes in the read and write paths of the device.

That's the closest explanation that i can see regarding disabling(some good/some bad) cache. :?

 

[1Tanker]

Well I'll be...I guess JK wasn't right after all. That does seem odd for Intel to disable the cache on those chips as the fail rate in the industry is about 5%. I know for a fact that AMD uses separate masks for the 512KB and 1MB L2 chips (it kind of has to.) So I guess Intel must have a problem getting all 4MB cache online (not likely,) they really busted their butts to get Conroe shot and out and thus only made 1 mask (more likely) or they only had one line open to make one die type of CPU and of course it was the full 4MB one (sort of likely, but less so that #2 because of the following.)

What this does say is that Intel has a ton of 65nm production capacity as it's willing to toss 4MB cache versions off as 2MB ones. I bet the guys in Sunnyvale are wishing that they had that luxury...

Both AMD and Intel had to do that, even if the cache was perfect e.g. Toledo when they stopped producing Manchester.
It's purely for market reason, but sometime the -ve outweighs +ve and that's the reason why Intel are coming out with 'native' Allendale(or whatever it's going to be called).

It's very easy to see this reason once you've experienced the Morgan/Throton/... eraI'd always heard that Celeron's were just P4's/PIII's with the cache chopped.

 

[1Tanker]

Side note, here is a nifty little explanation of cache in general, worth a read....

http://www.slcentral.com/articles/00/10/cache/index.php

Side side note -- I recall an interesting discussion where people often misconstrued electrons and signals in the platform as traveling at the speed of light, they do not and this site had a this to say, which ultimately leads to latency

Despite the common misconception that electricity flows at the speed of light, it does not. It certainly travels at speeds far greater than the speed of sound, but electrons flow at a finite speed that is much lower than that of light, and this fact has an impact upon the design and performance of processors. Why mention this? One must remember that computers only deal with information in low and high voltages of electricity. The speed of any given part of a computer is, at the very least, bound by the speed at which electricity can be transmitted across whatever medium it is on. This, in turn, shows us that the ultimate performance bottleneck is necessarily the speed at which electricity can move. This is also the case for cache.

Thanks Jack. Actually, this article sheds a little light on what they do.

Intel has taken a different approach with the P3 Coppermine. If one half of the cache is bad, but the other is fine, Intel just uses a laser to fuse the second half of the cache, and disable it. This saves the good part, and allows Intel to sell it as a Celeron. While they do this, they often just disable half of it anyway to get a Celeron to sell. This is actually cheaper than designing a chip with half the L2 cache, because Intel does not have to create different masks and such for another chip.

Further reading in this article brings up another interesting point(assuming things haven't changed that much in the 6 years since this was written).

One would think that AMD would do with their Duron and Athlon the same as Intel does with their Celeron and P3 Coppermine. However, they did not. When disabling a section of the cache, it also cuts the associativity proportionally with the fraction that was disabled. Thus the Celeron is only 4-way associative while from the same core. This reduces hit rate, and that's not something that AMD was willing to do. Also, simply disabling a part of a cache merely to have a product another market isn't an efficient use of fabrication capacity.

So, from what they're saying here, disabling cache actually incurs a slight performance penalty. This makes me wonder if, when Intel starts producing legitimate 2MB L2 Allendale's, will the non-disabling of cache create any performance differential(presumably better)? If that's the case, the Allendale's will be an even more attractive CPU, having more efficient cache, less transistors, probably some process updates(new stepping) and maybe even slightly lower pricing? I'm sure Intel will take in the savings brought about from less L2, rather than pass it along to the customer, though.