Just a peek at what next IEDM might bring on, while mouths keep shut from the big ones (IBM/Intel/AMD), until next mid-December.
Seems that Intel will continue to ride the bulk (sorry)... to use bulk Si alone (with the exception of Toshiba?!), in a somewhat straddling position (FD-SOI... how soon?):
High-performance 45 nm process — Toshiba (Tokyo) researchers will report on a complete high-performance bulk silicon technology for the 45 nm technology generation of logic devices. It marks the first appearance of ultrahigh-numeric aperture (NA) immersion lithography (NA=1.07) in a bulk logic process, and integrates it with many advanced device-building techniques. These include embedded DRAM, multiple silicon stressors (embedded SiGe, stress memorization, and dual-stress liners), a hybrid dual-damascene structure with a porous low-k dielectric (k=2.7), and a change in the way source/drain diffusion and extension is performed. The technology was used to build a very dense SRAM (0.248 µm2) with high drive currents for both nFET and pFET transistors.
Everyone else seems to go the SOI way (with improvements, of course); some (non-IBM/Intel/AMD) transistor's drive current records have been achieved:
Meanwhile, Freescale (Austin, Texas) researchers will describe a different low-cost 45 nm process. The key is a single metal gate, which is combined with a high-k gate dielectric. It demonstrated a record NMOS drive current of 1550 µA/µm. The process is a modified silicon on insulator (SOI) 65 nm technology that incorporates dual etch-stop layer stressors, a hafnium-based gate dielectric fabricated via atomic layer deposition (ALD), and a sputtered tantalum carbide gate electrode.
Best pFET performance — TSMC (Hsinchu, Taiwan) researchers studied the effect of multiple stressors on CMOS devices on (110) and (100) substrates. They also considered the effects of different channel directions. Among other results, they saw an 87% improvement in drive current for compressively strained pFETs with SiGe source/drain contacts on a (110) substrate with a <111> current flow orientation. Record pFET performance was demonstrated — Ion=900 µA/µm at Ioff=100 nA/µm and Vdd=1.0 V at 40 nm gate lengths. Since the current CMOS wafer orientation standard is a (110) surface with <110> current flow, these findings may lead to changes in standard CMOS processing.
This last one seems very interesting, since it was done in a pMOS transistor (which, due to "hole" behaviour, has a lower drive current than nMOS).
Now, I wonder what the big ones might bring up, process-wise, while the litho industry fine-tunes Immersion Lithography & other sophistications into the below-45nm nodes...