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Intel moving the memory controller on the die...

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November 28, 2006 12:03:07 AM

http://theinquirer.net/default.aspx?article=35892
I find this article a bit puzzling, seeing as it says Hyper Threading, which is not Hyper Transport is being changed, and that the memory controller comes onboard, but then it does not say anything about what will replace FSB... what will?(but it does say FSB is out the door by 2008).
November 28, 2006 12:48:14 AM

I believe they're rolling out reverse hyperthreading when they do the on-die memory controller.
November 28, 2006 12:55:14 AM

An Onboard memory controller is to replace the FSB. That´s it. And it´s not called HyperTransport but will be something similar (as in serial). Intel calls it CSI (common high-speed serial interconnect, i think).
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November 28, 2006 12:56:55 AM

What else is the eightball whispering? :?:
November 28, 2006 1:03:44 AM

Quote:
http://theinquirer.net/default.aspx?article=35892
I find this article a bit puzzling, seeing as it says Hyper Threading, which is not Hyper Transport is being changed, and that the memory controller comes onboard, but then it does not say anything about what will replace FSB... what will?(but it does say FSB is out the door by 2008).


I guess that multi-core for dummies book helped them out.
:oops: 

j/k

Intel knows that their scalability is crap with an FSB. I think it will take a rev or two to get to where HT3 will be then, though. They do have the core advantage (right now) but AMD has the platform advantage.
November 28, 2006 1:22:59 AM

A brief look at some common FSB speeds:
800MHz
1066Mhz
1333MHz
1600MHz
and 1800MHz is quite possible. What was that about scalability?
November 28, 2006 1:46:40 AM

Quote:
I believe they're rolling out reverse hyperthreading when they do the on-die memory controller.

Forgive me if I'm getting off topic of the OP, but I'm not understanding why the buzz about reverse HT. It seems like this would be nice to have around for all the games/programs out now that aren't optimized for two or more cores, but with more programs coming out in the future that will utilize multiple cores, why would something like this be needed in the long run?
November 28, 2006 2:26:40 AM

Quote:
A brief look at some common FSB speeds:
800MHz
1066Mhz
1333MHz
1600MHz
and 1800MHz is quite possible. What was that about scalability?

The problem with Intel's FSB is not speed/bandwidth, the problem is latency. The latency is much greater for the FSB than for HyperTransport. Neither the FSB or HyperTransport can be fully saturated because data from memory cannot be transfered that quickly. (There are some cases during bursts or memory reads that the bandwidth can be saturated for a brief time.)


Quote:
Forgive me if I'm getting off topic of the OP, but I'm not understanding why the buzz about reverse HT. It seems like this would be nice to have around for all the games/programs out now that aren't optimized for two or more cores, but with more programs coming out in the future that will utilize multiple cores, why would something like this be needed in the long run?

The theoretical Reverse Hyper-Threading would help older applications and also companies that can't put the time and money into making their software multi-threaded. You are right that as more mutli-threaded applications came out, the less Reverse Hyper-Threading would do (unless perhaps if the software is dual-threaded and you have a quad core processor).
November 28, 2006 2:44:30 AM

Quote:
An Onboard memory controller is to replace the FSB. That´s it. And it´s not called HyperTransport but will be something similar (as in serial). Intel calls it CSI (common high-speed serial interconnect, i think).


It's actually Common System Interconnect, as it was designed to allow Xeon and Itanium to use the same socket. It is serial-based though and is said to have even better latency than HyperTransport.

Impossible to say it is since exist not it does.
November 28, 2006 2:47:36 AM

Is this really news? I thought that Intel has pretty much stated that this was the plan for a while now. They still get good results from the FSB with C2D and don't need to change immediately. So, this is just kind of a natural transition as opposed to being forced by the competition. From my understanding anyways...
November 28, 2006 3:02:46 AM

Quote:
A brief look at some common FSB speeds:
800MHz
1066Mhz
1333MHz
1600MHz
and 1800MHz is quite possible. What was that about scalability?


Obviously the word scalability means what you decide. Scalabilitty refers to adding cores not bus speed. 8 1800MHz buses divdided amongst 4 sockets and 4 cores is a divisor not a multiplicand. Continually adding parallel FSBs is not cost effective. Opteron is still the fastest DB processor per core at most sizes. A lot of that is because of the scalability of HT.


Meaning that adding a processor adds interconnect bandwidth.


Oh yeah, there is JUST a 1333bus (nVidia) so 1600 and 1800 could be considered vaporware FUD dreamed up to make yourself seem informed.
What do you think?
November 28, 2006 4:01:30 AM

Quote:
Is this really news? I thought that Intel has pretty much stated that this was the plan for a while now...

I agree.

The InQ is presenting information that has been relatively well known for quite a while.

Socket transition and IMC on Intel chips have already been discussed here at ForumZ.

The only point that has yet to be determined is whether Yorkfield is going to be a single-die quad (as there's still some speculation around that it just might).
November 28, 2006 4:14:24 AM

Quote:
A brief look at some common FSB speeds:
800MHz
1066Mhz
1333MHz
1600MHz
and 1800MHz is quite possible. What was that about scalability?


I believe his comment may have been referencing his own scalability regarding his potential to expand his situational awarness beyond his AMD Line Of Sight reasoning. I love my AMDs, but if conroe and quadcore havent laid to rest his inability to accept the fact that Intels emory controller approach has been equal in terms of (current as well as future) performance to AMDs, then its just further proof that he is nothing more than a blind sniveling hord-o-phile.

Its amazing. Ive been out of town for 2 weeks, and I figured that maybe, as I am one of the bigger offenders when it comes to derailing threads in which Baron opens his suck hole, he would calm down a bit without me egging him on, but in the few moments Ive had to pop in a review a few threads, I see that was clearly a false hope. Que sera sera.

On a brighter note, congratulations to Jumping Jack on the birth of his son!!!! I guess I'll have to start refering to him as PJ for Papa Jack vs JJ.

Jack,
I trust all went well with the delivery and that momma and Bouncing Baby Jack are safely home.

Congratulations again :mrgreen: :mrgreen: :mrgreen:
November 28, 2006 4:18:17 AM

Quote:
A brief look at some common FSB speeds:
800MHz
1066Mhz
1333MHz
1600MHz
and 1800MHz is quite possible. What was that about scalability?


Obviously the word scalability means what you decide. Scalabilitty refers to adding cores not bus speed. 8 1800MHz buses divdided amongst 4 sockets and 4 cores is a divisor not a multiplicand. Continually adding parallel FSBs is not cost effective. Opteron is still the fastest DB processor per core at most sizes. A lot of that is because of the scalability of HT.


Meaning that adding a processor adds interconnect bandwidth.


Oh yeah, there is JUST a 1333bus (nVidia) so 1600 and 1800 could be considered vaporware FUD dreamed up to make yourself seem informed.
What do you think?
8O
Baron

You’re an intelligent person.
But I think your heat sink fell off
November 28, 2006 4:54:07 AM

Quote:
Is this really news? I thought that Intel has pretty much stated that this was the plan for a while now...

I agree.

The InQ is presenting information that has been relatively well known for quite a while.

Socket transition and IMC on Intel chips have already been discussed here at ForumZ.

The only point that has yet to be determined is whether Yorkfield is going to be a single-die quad (as there's still some speculation around that it just might).

As opposed to normally, where they just spew BS?

I'd say it's progress.

And Jack, I'd be curious to know whether they said it's going to have higher bandwidth and lower latency than HT3.0. That is, if you remember/can find the link.
November 28, 2006 5:06:35 AM

Okay, that's cool. Then I'm just gonna say BOTH HT3.0 and CSI will have more bandwidth than anyone in their right mind will EVER need. Fair enough?

Course, that's like saying no one will ever need more than 640K of RAM. But the point is still valid, for the moment at least.
November 28, 2006 5:25:34 AM

Quote:

The FSB replacement is referred to as CSI (not crime scene investiagation, this is what one must do after a BaronMatrix post).
Beautiful.. :trophy: :p  :p  :p  :p 
November 28, 2006 5:41:12 AM

I agree most aplications dont use the bandwidth we have now (my laptop has 533Mhz bus and seems to work fine for all the things it does) I guess some games could use more but I guess data centers and web servers can never get enough ?

My guess about CSI is that it will come out for servers first and then some time later for home use (my crystal ball is in "No Duh" mode)
November 28, 2006 6:43:17 AM

The article was about Hyperthreading, not Reverse HT...
While RHT or speculative multithreading is complicated and dubious, HT makes a lot of sense with the current paradigm shift towards explicit multithreading programming.
For example, making a full 6-scalar core wouldn't make much sense, since in most cases/apps you won't find such a parallelism in the instructions that you want to execute.
But let's say that you do a double threaded, 4 issue, 6-scalar execution engine with HT.
With this i mean, you can process up to 6 instructions in parallel, but a single thread can only issue 4 (both threads together issue up to 8 )... with HyperThreading, you'd be able to feed the 6-scalar execution engine with a much higher utilization rate than with a single thread, because sometimes one thread would be able to execute more instructions in parallel, sometimes the other, sometimes both, etc.
November 28, 2006 7:14:49 AM

Common System Interconnect it is! I guess is got that a little messed up. And i´m quite curious to see how well it works out for intel.
November 28, 2006 7:20:40 AM

Quote:


Intel knows that the FSB will ultimately need to be replaced, but the scalability of the FSB is certainly allowing them to hold the crown in all market segments.... or have you missed the headlines.


In a two Processor system it may work out. But there is also cost efficiency. The cost may not become a real factor in a 4P system, since it´s probably neglectible compared to the cost of the other hardware and software for servers. But once you up the processor count once more, Intel is out of the competition. Even in a 4P system, the additional cost is something intel can´t afford if they want to dethrone Opteron. While i know that the supercomputer market only accounts for a small share of the whole processor market, it´s where intel has difficulties.
November 28, 2006 7:38:50 AM

Then there's the fact that supercomputers, as well as servers, cost far more than your average, or even gaming, computer. So while they're still a small percentage of the market in numbers, and even a small percentage in money (most likely), they still count for a heck of a lot.

Jack's not saying the FSB is good or anything, he's just saying Intel's managed to make it this far with it, and the headlines prove they did a good job (so far).
November 28, 2006 11:02:32 AM

Quote:
No where does the definition of scalability require the platform to increase core count to be considered scalable thus possess scalability. What you mean is that adding cores using AMDs NUMA approach results in higher aggregate bandwidth, and as application needs rise can scale better.


Why don' you go back to your hole. The word SortedList (.Net class) isn't even in the dictionary so that means nothing. When talking about PCs you know what scalability is, but keep letting everyone know I've gotten to you.
November 28, 2006 11:38:20 AM

Quote:
I believe they're rolling out reverse hyperthreading when they do the on-die memory controller.


There is not point implementing "reverse hypertherading" it is a total waste of die space that could be *far* better used for something else.

Sure it is a nice dream, but by 2008 most developers (with a clue) will be making heavily threaded applications designed for multi-core systems.

There is absolutely no point implementing "reverse hyperthreading" in 2008.

It isn't technically impossible, but it is far more difficult than most people think to combine multiple CPU pipelines, registers, etc into one 'logical' pipeline for the 'minority of software' (given the 2008 timeframe).

Anything that isn't threaded by then is unlikely to require threading to give decent performance, or just simply would not scale (other bottlenecks).

I've thought about how cool it would be, so I did some research on it, the educated conclusion in every case was that it was a waste of a large portition of die space that could go to cache, more cores, and/or other features.

Intel Xeon 5100 systems use a dual 1333 FSB, typically with larger caches and get more utility (via prefetching, etc) out of their 'slower' interface to RAM.

AMD Opteron 200/2000 systems use ccNUMA and can aggregate the performance (I used to run an Opteron 270 with ccNUMA it was alright), but the smaller caches in many applications let to lower utility of the higher FSB (nTune has a FSB throughput indicator).

The AMD system typically got around 70% utilisation of its 'FSB' (for lack of a better definition, but anyone reading this knows what I mean).

The Intel system typically got around 83% (give or take) of its dual FSB.

Sure when cache hit rates get low the Opteron scaled better, but since cache hit rates are usually in the order of 60%+ in most tests the Intel rig comes out on top. Not always by a large margin, and in some very intensive tests the Opteron comes out on top.

Price and Longtivity (FB-DIMMs will scale to higher density than Reg ECC DDR2 DIMMs) the Intel system usually wins out. (Then bear in space, power consumption, performance ber cubic foot, etc).

However I'll admit it is a close race, and AMD don't need to add a 4th pipeline to get back into the lead, esp in 8-way (8 core) and above systems.


Bear in mind currently 2 of my 3 systems are AMD, as even I will be transitioning gradually.

- Turion 64 laptop (Only x64 mobile on the market at the time, Core Duo was not established and only x86-32, and Pentium M didn't look as cost effective)

- AMD Athlon 64 X2 - 2.4 GHz, 2 x 512 KB L2 cache, Dual-Ch DDR2-800

- Intel Core 2 Duo E6600 - @ 3.0 GHz / 1333 FSB. Also decked out.


I like to keep a 45/45/10 or 40/40/20 balance (Intel / AMD / Other + Mobile) using budget and performance/dollar as my 'splitter'.

November 29, 2006 12:40:35 AM

Quote:
Common System Interconnect it is! I guess is got that a little messed up. And i´m quite curious to see how well it works out for intel.


I'm unsure if this was already addressed in previous posts but, anyway, it was presented by Intel & IBM, at last IDF: "Geneseo".
Though not a replacement for the current FSB, it's an improvement over PCIe, on what concerns bus interconnects' standards and, like CSI, is integrated in the PCI-SIG.

http://www.crn.com/showArticle.jhtml?articleID=193006380

"Geneseo" is currently supported by:
Quote:
Adaptec Inc., AGEIA Technologies Inc., Altera Corporation, Broadcom Corporation, Celoxica, Cisco Systems, ClearSpeed Technology, Dell, EMC Corporation, Emulex Corporation, HP, Integrated Device Technology Inc., Lecroy Corporation, Linux Networx, LSI Logic, Mellanox Technologies, Myricom, NetEffect, Novell, NVIDIA, PLX Technology, PMC-Sierra, QLogic, Sun Microsystems, Synopsys, Tektronix, Xambala Inc., Xilinx Inc. and Xtreme Data.

http://www.intel.com/pressroom/archive/releases/20060927comp_a.htm


Cheers!
November 29, 2006 1:09:17 AM

Quote:

The only point that has yet to be determined is whether Yorkfield is going to be a single-die quad (as there's still some speculation around that it just might).


Intel's roadmap lists the Yorkfield as having 2x6mb of L2 cache, from that bit of detail it's sounding like we wont be seeing the 'single die quad core' just yet.
November 29, 2006 1:17:34 AM

That Yorkfield sounds like two Wolfdale dies on the same package. Basically, a 45nm Kentsfield with more cache.

From what I've heard, Bloomfield is supposed to be Intel's first "native" quad-core, but that may have changed...
November 29, 2006 1:27:49 AM

Didn't see that one the roadmap... any idea when thats meant to arrive?
November 29, 2006 5:09:50 AM

"Converged quad core parts are Nehalem." - that's 45 nm
http://theinquirer.net/default.aspx?article=36010
And I have a question, I read, a while back about SOI and the memory controller and hyper transport, and in order for Intel to adopt something AMD was using, Intel would need to adopt SOI. Any idea if this is the memory controller or if this is hyper transport? And any proof to these statements.
November 29, 2006 5:12:00 AM

Let's give you a lesson in reliability of sources:

Lies
|
INQ
|
|
|
|
Chinese Media
|
American Media
|
Scientific journals
|
The Truth

That would be Z-RAM, a new cache technology that exploits a property of SOI allowing cache 6 times as dense as 6-transistor classic SRAM cache.
November 29, 2006 5:50:01 AM

I thought that reverse hyperthreading was actually virtualization. Does anyone have the right answer?
November 29, 2006 7:53:35 AM

Good to see you again Joset.

I'll need to see what other threads you're reading and/or posting in.

I am back :wink:
November 29, 2006 9:07:03 AM

Quote:

I'm unsure if this was already addressed in previous posts but, anyway, it was presented by Intel & IBM, at last IDF: "Geneseo".
Though not a replacement for the current FSB, it's an improvement over PCIe, on what concerns bus interconnects' standards and, like CSI, is integrated in the PCI-SIG.

http://www.crn.com/showArticle.jhtml?articleID=193006380

"Geneseo" is currently supported by:
Adaptec Inc., AGEIA Technologies Inc., Altera Corporation, Broadcom Corporation, Celoxica, Cisco Systems, ClearSpeed Technology, Dell, EMC Corporation, Emulex Corporation, HP, Integrated Device Technology Inc., Lecroy Corporation, Linux Networx, LSI Logic, Mellanox Technologies, Myricom, NetEffect, Novell, NVIDIA, PLX Technology, PMC-Sierra, QLogic, Sun Microsystems, Synopsys, Tektronix, Xambala Inc., Xilinx Inc. and Xtreme Data.

http://www.intel.com/pressroom/archive/releases/20060927comp_a.htm


Cheers!

And again something i didn´t know. I´m curious why ATI isn´t on that list though.
November 29, 2006 11:26:15 AM

Quote:
Good to see you again Joset.

I'll need to see what other threads you're reading and/or posting in.

I am back :wink:


Thanks, good to see you too.

I've also been too busy; not having contributed much to the forum, lately; merely replying, occasionally.


Cheers!
November 29, 2006 11:42:45 AM

Quote:
And again something i didn´t know. I´m curious why ATI isn´t on that list though.


My intent was to give some perspective, as well. IBM's too heterogeneous in partnership behaviour, being THE technology giant, to be bounded, exclusively, to this or that chip maker company (of course, I'm referring to the IBM/AMD partnership); actually, ATi has used a 'proprietary' ring-like bus in its latest graphics chips, much like Cell's implementation; I wonder how much cooperation have been online, between ATi & IBM, outside any wider partnerships and even, how much it contributed to the merging...

My uneducated speculation...


Cheers!
November 29, 2006 12:44:16 PM

Quote:
Okay, that's cool. Then I'm just gonna say BOTH HT3.0 and CSI will have more bandwidth than anyone in their right mind will EVER need. Fair enough?

Course, that's like saying no one will ever need more than 640K of RAM. But the point is still valid, for the moment at least.


This is a fair statement..... very fair. And I like your analogy with 640K of RAM :)  :)  gotta chuckle at that one.

Another way to put it --- we have enough band width until there is not enough :) 
OF course, but intel HAS to switch to a serial interface like HTT because it also needs some testing and experimenting like AMD did, they can't just switch to it instantly.
November 29, 2006 12:57:59 PM

Quote:
And again something i didn´t know. I´m curious why ATI isn´t on that list though.


My intent was to give some perspective, as well. IBM's too heterogeneous in partnership behaviour, being THE technology giant, to be bounded, exclusively, to this or that chip maker company (of course, I'm referring to the IBM/AMD partnership); actually, ATi has used a 'proprietary' ring-like bus in its latest graphics chips, much like Cell's implementation; I wonder how much cooperation have been online, between ATi & IBM, outside any wider partnerships and even, how much it contributed to the merging...
Cheers!

My uneducated speculation...

You've sparked my curiosty, where does ATI use the "ring-like" bus?
November 29, 2006 6:33:54 PM
!