Amd Altair FX

[RandMcnally]

Just a quick post, it looks interesting, but I won't be buying a cpu for many a months, so the next time I buy is when quad cores are the price of a cheap dual core. Anyways, I just find this interesting...
http://theinquirer.net/default.aspx?article=36003
http://theinquirer.net/default.aspx?article=36017

It sounds like a very fast beastly quad hearted heifer.

 

[lambofgode3x]

Just a quick post, it looks interesting, but I won't be buying a cpu for many a months, so the next time I buy is when quad cores are the price of a cheap dual core. Anyways, I just find this interesting...
http://theinquirer.net/default.aspx?article=36003
http://theinquirer.net/default.aspx?article=36017

It sounds like a very fast beastly quad hearted heifer.

when you read anything from the inquirer take everyting you read with a grain of salt. they are known to just make stuff up or exagerate a little bit.

 

[randomizer]

Very true, companies will often skew results and info in their favour, which is expected really since they are out to make money not tell the truth.

 

[Pippero]

The 6MB cache thing doesn't make sense to me.
First it says that "When we say dedicated, it means that each CPU has 2 MB of L2 memory, total of 4MB of L2 memory plus 2MB of shared L3." but this is a 4 core CPU, so the total L2 should be 8 MB.
But even if the total L2 is 4MB, then a 2MB L3 can't be inclusive.
If the L3 is exclusive, it has to exchange a lot of info with all L2 caches, and it doesn't help at all with communication/bandwidth among the cores.

 

[gOJDO]

I am 99.99999999999999999999999999% sure, the article is pure BS.
Fuad has copy-pasted something form the chinese sites like HKEPC, without understanding it. I think he saw total 2MB of L2, which means 512kB L2 per core and he translated inot 2MB of L2 per core.
Like you said, the shared L3 must be larger than the exclusive L2 cache per core. For example, if two cores needs to write back data from the L2 to L3, it would be impossible if the data from both cores is larger than L3 capacity. To be effective the L3, which AMD are calling victim cache, has to be large as L2 caches together.

 

[Doughbuy]

So uh... what happened to PPW? That huge cache looks like it's going to suck up the ol electricity...

I thought increasing cache was just an Intel thing and AMD laughs at them for that... shrug. And do we really need 6 mb of cache?

 

[Arrowyx]

It certainly sounds interesting but the Inquirer doesn't really have any sort of good track record on things like this. If it does end up true, well good. If not, no biggie to me, just another mistake in the long history of Inquirer mistakes.

 

[RandMcnally]

Hehe, don't think I believe all that I read, it's just that the Inquirer has no reputation to waste so they throw out future speculation stuff when I cannot find another site that really has details about future plans.

 

[TechnologyCoordinator]

Leave it to the Inq to get basic math wrong.

 

[tamalero]

Just a quick post, it looks interesting, but I won't be buying a cpu for many a months, so the next time I buy is when quad cores are the price of a cheap dual core. Anyways, I just find this interesting...
http://theinquirer.net/default.aspx?article=36003
http://theinquirer.net/default.aspx?article=36017

It sounds like a very fast beastly quad hearted heifer.

Just a friendly word of advice, the Inquirer has about a 50/50 track record on providing real vs imaginary information.

They often need to retract or correct what they post. Be careful what you believe from them.... it is nothing more than an AMD propoganda machine for the most part.

Also, second word of friendly advice --- challenge what you read when coming from the respective companies. When looking at data produced by either Intel or AMD (benchmarks for example), always ask --- is this valid, can I (if I wanted to) reproduce the results given the details they provide.

wherent you the one that was bitching a few ago about how AMD lacked of "marketting" ?
Hilarius. "propaganda machine"
dont mistake Intel ( who has a huge propaganda machine ) with AMD ( who lacks of .. )
but agree on the inquirer thing

 

[randomizer]

Its pretty hard to mistake intel for amd. Do you see any amd ads on tv? Or dell ads with amd chips? Hey has anyone seen the new HP Pavillion laptop ad? Its a real mouthful, "(blah blah blah)with intel centrino duo mobile technology". Now they've added in the "duo" to that overused line as well.

 

[RandMcnally]

Do you see any amd ads on tv? Or dell ads with amd chips?

Yes actually, to both, and recently.

 

[NMDante]

True.

I just saw a Dell ad for a Turion laptop. Actually it was "a Dell laptop, powered by an AMD Turion processor" as the voice stated.

It was the first time I had ever seen AMD promoted on network TV (I think I was watching Heroes or MNF, at the time).

The thing is, I was expecting the Intel "ding, ding, ding, ding" sound at the end of the commerical.

 

[4745454b]

I don't see the gains to be had by increasing cache. Intel uses cache to compensate for the lack of an IMC. AMD doesn't need lots of cache because it can fetch info from ram faster then Intels CPUs. AMD needs to rework the current K8 CPU to retake the lead, not increase cache amounts.

 

[RandMcnally]

I don't see the gains to be had by increasing cache. Intel uses cache to compensate for the lack of an IMC. AMD doesn't need lots of cache because it can fetch info from ram faster then Intels CPUs. AMD needs to rework the current K8 CPU to retake the lead, not increase cache amounts.

Altair is a reworked cpu and in the reworking it got more cache.

 

[4745454b]

Altair is a reworked cpu and in the reworking it got more cache.

Gee, thanks for the tip. I never would have figured that out...

What I was trying to say was that adding cache, as I understand CPUs, is that high amounts of cache aren't really needed for AMD CPUs. Here, here's a link.

http://www23.tomshardware.com/cpu.html?modelx=33&model1=487&model2=489&chart=177

Notice that the diffence between the 3700 San Diego and the 3500 Venice is 5seconds. The 3700 has twice as much L2 cache as the 3500. Look what chips are right above that however. The 3400 and 3700 that, although they have half as much L2 cache as the 3700 San Diego, are able to perform this test faster due to their higher clock speed. (30 seconds faster or better.)

I know they reworked the chip, but they better have done more then just add cache. If they didn't, I doubt they'll gain much on Intel.

 

[Pippero]

First, i believe the Inquirer got it all wrong, and the cache of these CPUs will be (64KB L1 + 512KB L2)x4 + 2MB L3.
At most, it could be (64KB L1 + 1MB L2)x4 + 2MB L3.
Second, the new architecture will be using much more bandwidth than the previous one: it can load 2 x 128bit data per clock, and it can process them too, thanks to the new SSE / FP engine.
So in computationally intensive application, K8L can crunch up to 100% more data than K8; of course that doesn't mean a 100% gain accross the board, far from it, except perhaps in a few synthetic benchmarks.
Also the L3 cache will help a lot with multithreaded applications, with all cores working in the same memory area.
I stand firm that, with 2MB of L2 per core, the L3 wouldn't make any sense.

 

[qcmadness]

I am 99.99999999999999999999999999% sure, the article is pure BS.
Fuad has copy-pasted something form the chinese sites like HKEPC, without understanding it. I think he saw total 2MB of L2, which means 512kB L2 per core and he translated inot 2MB of L2 per core.
Like you said, the shared L3 must be larger than the exclusive L2 cache per core. For example, if two cores needs to write back data from the L2 to L3, it would be impossible if the data from both cores is larger than L3 capacity. To be effective the L3, which AMD are calling victim cache, has to be large as L2 caches together.

The caching system is debatable as AMD traditionally uses exclusive caching system.

The L3 may be used as the bridge for data exchange between cores.

 

[RandMcnally]

I do believe the Inq calculated it wrong. There are a lot of architectural changes to the cpu, it's a reworked architecture. There are rumors that the inclusion of L3 cache is better for virtualization on the quad core front.

 

[evilr00t]

Show me proof that the rumors are true.

 

[RandMcnally]

Show me proof that the rumors are true.

Rumor
1. a story or statement in general circulation without confirmation or certainty as to facts

 

[evilr00t]

FUD, n.

FUD is the fear, uncertainty, and doubt that IBM sales people instill in the minds of potential customers who might be considering Amdahl products. Ripped from Wikipedia, word for word.

 

[MU_Engineer]

Well, enough places have said that AMD will put 2MB L3 cache on the chips. I can easily see the cache distribution being 6MB as AMD may very well put 1MB L2 per CPU, and 4 1MB L2s plus that 2MB shared L3 would make 6MB in total.

But I thought that I also read that AMD was going with 512KB L2s per core, so that would make the L3 cache 4MB rather than 2MB...I dunno. It's the Inquirer- they have been known to be wrong once in a while

 

[evilr00t]

6MB of cache? That just doesn't make sense given that there's a dieshot of Agena floating around somewhere, with annotated components. The area used by the L3 cache is roughly 4x the size of the L2 for each core. Given the L3 cache is 2MB, the rest of the cache would be 2MB as well, total, for 512K cache per core.

JumpingJack even counted up the surface area for Parrot in some long, deceased, decaying thread.

 

[MU_Engineer]

That's what I hinted at. Either the Inquirer could be wrong or AMD has twiddled with the design of the chip. Since AMD demonstrated a quad-core chip today, I doubt that they twiddled with the design much.