Sign in with
Sign up | Sign in
Your question

AMD questions current multi-core trend

Last response: in CPUs
Share
December 14, 2006 3:45:05 PM

Article:

http://www.tgdaily.com/2006/12/14/amd_questions_multi_c...

As I've said in a couple other posts, I really hope this type of thinking works out well for AMD. The first thing I thought of when I read about multi-core processors was how great this would be for Computational Fluid Dynamics, and now I'm looking at AMD's Fusion and thinking about how how nicely floating-point performance boost would do as well. Combine the two in a single package, and the average Joe can afford to build a workstation for serious number crunching.

Yes, this stuff is still way down the pipe, but what are the perspectives from you in the enthusiast and gamer segment? If K8L doesn't bring AMD back on top, will Fusion?

Edit: replaced typo "K9L" with "K8L"
December 14, 2006 4:29:18 PM

Quote:
i would question it to if i didnt have a competative product.
they are just trying to stall so they lose market share slower.
the potential of multicore systems is great. my guess is they are forseeing supply issues by making multicore products and want to try to dodge the bullet


Interesting enough the same arguments were said about AMD during the Ghz war.
December 14, 2006 4:36:20 PM

Quote:
the potential of multicore systems is great. my guess is they are forseeing supply issues by making multicore products and want to try to dodge the bullet


The potential is great in systems that can really use seriously multi-threaded apps. Despite the capability of more threads, the average home user really isn't going to know what to do with much more than 6-8 cores. Too many programs will need to be entirely re-written to properly take advantage of a general processor, where as a speciallized one could do a far better job at it's task. Cell might not look to good right now, but it's a decent start down a path I see no way to avoid.
Related resources
December 14, 2006 4:38:43 PM

To some extent though AMD are right..... we can't keep on going the way we are with increasing core count, since SMP is in a way a specialised form of processing anyway. There will be some applications that can never realistically use multiple cores, and for others there will come a point where you can't utilise any more cores. Without a major paradigm shift in programming languages this will remain the case.

Personally I think AMD is along the right lines with suggesting having application specific processors in the future, only I would go further and would suggest looking into creating a CPU/FPGA hybrid, where there are a limited number of fixed general purpose CPUs on chip, with a large reconfigurable FPGA that could synthesise application specific processors on the fly depending upon the tasks you are currently executing.
December 14, 2006 4:40:55 PM

Quote:
Article:

http://www.tgdaily.com/2006/12/14/amd_questions_multi_c...

As I've said in a couple other posts, I really hope this type of thinking works out well for AMD. The first thing I thought of when I read about multi-core processors was how great this would be for Computational Fluid Dynamics, and now I'm looking at AMD's Fusion and thinking about how how nicely floating-point performance boost would do as well. Combine the two in a single package, and the average Joe can afford to build a workstation for serious number crunching.

Yes, this stuff is still way down the pipe, but what are the perspectives from you in the enthusiast and gamer segment? If K8L doesn't bring AMD back on top, will Fusion?

Edit: replaced typo "K9L" with "K8L"
There is no K9L. AMD is going from K8L to K10. :wink: They probably foresee too many dog jokes(K-9). :p 

Edit: Disregard due to OP's edit. LOL
December 14, 2006 4:42:41 PM

I like the CPU/FPGA concept. Have there been any rumors of development in this direction?
December 14, 2006 4:46:29 PM

"K8L" is Intel's designation for AMD's "Stars" processors (and server/workstation quad-core cpu's). Why be fussy unless you want to get real fussy. lol. I'm still trying to figure out how the price difference between a 1900 and stream processor is so great, myself.
December 14, 2006 4:48:03 PM

I am very intrigued. This is something that AMD is doing right in my opinion. What if AMD pulls this off by the end of the decade and all Intel has to offer is more and more cores. AMD users could brag about how fast their system is and Intel users could brag about how many idle cores they have in their system.

I don't know what this will do for gamers though. I can definitely see some major advantages in low-end, midrange, and the mobile market.
December 14, 2006 4:48:15 PM

Ah, yes... a major drawback I hadn't considered is the departure from x86 to accomplish this. Would it be possible to maintain the x86 arch in the general purpose cores and then have some smart drivers handle the extra processing units (FPGA)... the extra units would be slaves to the general cores.
December 14, 2006 4:49:12 PM

It's not a AMD specific Idea, lol. Intel plans the same thing, in about the same timeframe. They just need to cattle-prod their GPU team(s).
December 14, 2006 5:07:07 PM

??? Everything I've seen shows Intel somehow leaked the K8L name. AMD was undecided between using Roman Numerals "V" for five as in K8.5 and "L" for fifty, K8.50. I still think they'd should have used K9 myself. That's kickass!
a b à CPUs
December 14, 2006 5:13:13 PM

This is another example of AMD thinking out of the box and anticipating the realities of the future. A similiar move by AMD resulted in two things; 1) AMD went with the IMC because they saw they limitations and eventual demise of the north bridge/front side bus design, and 2) chose to integrate Hypertransport as the interconnect standard. Say what you will about this strategy but remember that Intel is moving to an IMC as well as their own high speed hypertransport-ish interconnect standard.

I imagine that the Fusion design is going to open a lot of doors and create a number of revenue streams for AMD. It will be interesting to see how these chips are implemented in consumer electronics as well as computers.
December 14, 2006 5:15:20 PM

Quote:
??? Everything I've seen shows Intel somehow leaked the K8L name. AMD was undecided between using Roman Numerals "V" for five as in K8.5 and "L" for fifty, K8.50. I still think they'd should have used K9 myself. That's kickass!


K8V is used in motherboard names, that's why L was chosen.

K9 would have been awesome, WOOF!
December 14, 2006 5:18:01 PM

Not to my knowledge - I've come up with the idea myself as I've done quite a bit of work with FPGAs. One development that makes this more viable now is that you can now partially reconfigre FPGAs, which would make it easy to reprogram a specific part of it. If I've come up with the idea though you can be sure the boffins at Intel and AMD will be investigating it - the 80 core demo Intel did a while back was on an FPGA.

@beerandcandy - I dont see how this is proprietary any more so than the K8 and Core 2 are proprietary - both accept x86 instructions, as would the CPU/FPGA hybrid, just the internal implementation would be different. For example, if you were executing a lot of SSE instructions, a controller on the CPU would detect this, and synthesise some co-processors that can handle SSE instructions more effectively. It's still processing x86 instructions, the same as current CPUs.

You'd need a fancy network on chip architecture to deal with this, I've had a think through some ideas myself but it's not an easy problem to solve. The potential performance speedups you could get if the really smart guys at AMD/Intel get it working though could be huge.
December 14, 2006 5:30:25 PM

Quote:
Article:

http://www.tgdaily.com/2006/12/14/amd_questions_multi_c...

As I've said in a couple other posts, I really hope this type of thinking works out well for AMD. The first thing I thought of when I read about multi-core processors was how great this would be for Computational Fluid Dynamics, and now I'm looking at AMD's Fusion and thinking about how how nicely floating-point performance boost would do as well. Combine the two in a single package, and the average Joe can afford to build a workstation for serious number crunching.

Yes, this stuff is still way down the pipe, but what are the perspectives from you in the enthusiast and gamer segment? If K8L doesn't bring AMD back on top, will Fusion?

Edit: replaced typo "K9L" with "K8L"



I totally agree with that assessment. I mean you can only add so many cores to a die before you need more bandwidth and wider data paths and more power.

By modularizing it is possible to use the same basic parts to build different levels of computational power.

I'm sure this doesn't mean that there is no possibility of an 8core AMD bvut it will more likely consist of 4 CPU cores and 4 GPU cores.

As far as Barcelona I can only say that in Sept AMD said it was 60% faster and then in Dec AMD said it was 70% faster than Opteron.

I guess next month it will be 80% faster. I wonder if they will hit 100% faster by July. That would definitely be close to Clovertown. Fusion won't help with desktop and productivity apps, but only HPC type apps (CFD, FEA, CAD, etc), though those are the best use of a server so I'd have to say that with the combination Intel is back in the back seat of perf.

I would love to see AnSYS running on QFX or Agena FX. I bet MicroStation would fly too.

I guess you're a MechEngr?
December 14, 2006 5:36:08 PM

Quote:
i would question it to if i didnt have a competative product.
they are just trying to stall so they lose market share slower.
the potential of multicore systems is great. my guess is they are forseeing supply issues by making multicore products and want to try to dodge the bullet


Maybe AMD should change its name to OCD:

"We've got 65nm... no 90nm... Quad FX is the way to go... but we want to 'Fuse' the GPU... do you have any chocolate... what time is it in Nepal..." :lol: 
December 14, 2006 5:44:18 PM

Quote:
i would question it to if i didnt have a competative product.
they are just trying to stall so they lose market share slower.
the potential of multicore systems is great. my guess is they are forseeing supply issues by making multicore products and want to try to dodge the bullet


From K8's experience, AMD has headed the right direction, leading Intel for 3 or more years.

Hypertransport and integrated memory controller are proved to be better than traditional front side bus and external memory controller, especially in server space.

Also, multi-core symmetric processing is heading to its end.
The second fastest computer in the world now is consisting two types of processors already.
December 14, 2006 5:50:29 PM

This quote from the article worries me:

"If AMD has its way, than we could be going from a universal computing device today to very specialized and targeted hardware by 2009 and beyond."

I don't want specialized targeted hardware. That means that the system I buy to work on won't be the one I play on or the one I watch media on. I'm spending enough money on computer equipment as it is. That is the exact opposite direction that should be taken. Like the average buyer, I don't care if it's Fused CPUs/GPUs or calculating squirrels on crystal meth that are making my PC go. I want it to do everything I can throw at it, I want it to do it fast as lightning and I want it to cost less than my alimony!
December 14, 2006 5:52:17 PM

I can't think of much that a computer consisting of one quad core cpu, one decent "stream" processor, and one Ultra Sparc, couldn't do. And that would probably be somewhat feasable if you could afford the silicon for it.
December 14, 2006 5:57:53 PM

Quote:
I can't think of much that a computer consisting of one quad core cpu, one decent "stream" processor, and one Ultra Sparc, couldn't do. And that would probably be somewhat feasable if you could afford the silicon for it.


Not doubting that one bit. In fact your description's got me drooling on the keyboard. But what is this deal with AMD going to ultraspecialized hw?
December 14, 2006 6:13:37 PM

AMD questions current multi-core trend? Pfft. Multicore APU FTW!

Come on, this is just another short-term answer to a long-term problem of maintaining Moore's Law. Though I think AMD is right on with that, I want more news about moving off of silicon.
December 14, 2006 6:57:41 PM

Yeah, a brand new architecture destroys one that is nearing half a decade old. Good job Intel.
December 14, 2006 7:00:46 PM

I don't thonk AMD's going the way of ultra specialized proccess so much as allowing mix and match choices for the consumer. That way the end user gets to integrate whats aplicable to him/her. After seeing how many programs it takes to stress 4 or 8 cores, and considering the lag in multi-threaded programs available, and the complexity of programming for even more cores, it makes more sense in the near term (4-5 years) to streamline the platforms/CPUs for whats realistic (here come the flames) and extract the most performance with proccesses available now. :oops: 
IMO it boils down to more choices, more power, and hopefully less money wasted for things I don't use(or can't).
BTW, Any idea how many manhours it takes to program threads for 8 CPU as opposed to 4, anyone?
Then again what do I know. I'm a noob.
December 14, 2006 7:09:48 PM

Quote:
BTW, Any idea how many manhours it takes to program threads for 8 CPU as opposed to 4, anyone?


With the current trends toward multi-cores, they should be developing tools that can dynamically allocate processes to different cores automatically very efficiently, so it (hopefully by that time) take the exact same amount of time. But when you talk about the software development of today, I have no idea. Twice as long? Four times as long?
December 14, 2006 7:21:55 PM

Quote:
From K8's experience, AMD has headed the right direction, leading Intel for 3 or more years.

Hypertransport and integrated memory controller are proved to be better than traditional front side bus and external memory controller, especially in server space.


ok if what you say is true then please explain these benchmarks.

http://www.tomshardware.com/2006/07/14/core2_duo_knocks...

clearly intel still using its old limited bandwitdth FSB destroys amd

Would you mind re-reading my post? :wink:
December 14, 2006 7:35:57 PM

I'm building a 10 CPU C2Q600 cluster for CFD in January 8)
December 14, 2006 7:51:27 PM

Not as nuts as the people who defended the P4 drive me, I'm sure.
December 14, 2006 7:57:22 PM

The fact that Intel is moving to an IMC and a HyperTransport-ish technology is proof enough that there are limitations to the FSB and Nortbridge technologies. Perhaps Intel is able to squeeze a bit more performance out of the FSB right now, enough to smash current/past gen IMC, but when Intel finally goes to the IMC, AMD will have a tech that is several years more mature and much more experience with dealing with whatever nuances are created when such a tech is implemented.

The FSB will be hitting the wall soon. AMD saw that, perhaps because their chips are more prone to hitting that wall sooner, and moved to a more efficient setup. Current raw performance is not in question here, its quite obvious that today's implementations are still on par and better than the IMC implementations of yesterday. Its the future of the tech that is in question and it is in the future when IMC will show its real strengths and the many years old FSB will show its weaknesses (perhaps spectacularly) if Intel holds on to it long enough.

It is in the future where IMC destroys the FSB. It is the now where they are the same. It is the past where IMC destroyed the FSB. It is also the past where FSB was the only thing, and IMC didn't exist.

There are no flames needed here.
December 14, 2006 7:58:47 PM

Quote:
Not as nuts as the people who defended the P4 drive me, I'm sure.


Wasn't around here for that one. I bet it was hilarious.
December 14, 2006 8:02:42 PM

Quote:

yes you are right you were refering to servers
here is your link
please explain why you post that amd is doing better than intel using HT and IMC when its not true

http://www.tomshardware.com/2006/10/26/intel_woodcrest_...


Simple question, why Intel would like to use CSI for Xeon starting form 2008?
December 14, 2006 8:06:23 PM

Quote:
new system architecture

Certainly no.
December 14, 2006 8:08:26 PM

Quote:
This quote from the article worries me:

"If AMD has its way, than we could be going from a universal computing device today to very specialized and targeted hardware by 2009 and beyond."

I don't want specialized targeted hardware. That means that the system I buy to work on won't be the one I play on or the one I watch media on. I'm spending enough money on computer equipment as it is. That is the exact opposite direction that should be taken. Like the average buyer, I don't care if it's Fused CPUs/GPUs or calculating squirrels on crystal meth that are making my PC go. I want it to do everything I can throw at it, I want it to do it fast as lightning and I want it to cost less than my alimony!



I think you're taking the concept too far. What they mean is that the same building blocks for a PDA will apply to the PC and MP3 /MPEG player.

The first fusion GPU will be in a laptop as integrated graphics. They won't be able to really achieve "Fusion" with a "game-level" product until 45nm when the process size will allow for the same 64 shaders on the die.

This will of course need the higher bandwidth of 2GHz DDR3 so that's a ways off yet.

I expect Barcelona to ship with an HTX "Stream" Processor, and the refresh in Jan 08 should see a socketed version using an eDRAM buffer like Xbox360.

There are already PCIe coProcs and the market just needs to increase in the HPC space and cHT will be a staple in servers before CSI even comes out. Even PCIe 2.0 won't have enough interconnect bandwidth to compete with HT3.
December 14, 2006 8:09:56 PM

Quote:

I think you're taking the concept too far. What they mean is that the same building blocks for a PDA will apply to the PC and MP3 /MPEG player.

The first fusion GPU will be in a laptop as integrated graphics. They won't be able to really achieve "Fusion" with a "game-level" product until 45nm when the process size will allow for the same 64 shaders on the die.

This will of course need the higher bandwidth of 2GHz DDR3 so that's a ways off yet.

I expect Barcelona to ship with an HTX "Stream" Processor, and the refresh in Jan 08 should see a socketed version using an eDRAM buffer like Xbox360.

There are already PCIe coProcs and the market just needs to increase in the HPC space and cHT will be a staple in servers before CSI even comes out. Even PCIe 2.0 won't have enough interconnect bandwidth to compete with HT3.


You imagination is fascinating but I don't think that would be true.
December 14, 2006 8:19:56 PM

Quote:
BTW, Any idea how many manhours it takes to program threads for 8 CPU as opposed to 4, anyone?


With the current trends toward multi-cores, they should be developing tools that can dynamically allocate processes to different cores automatically very efficiently, so it (hopefully by that time) take the exact same amount of time. But when you talk about the software development of today, I have no idea. Twice as long? Four times as long?


It all depends on what the threads have to do. If they have to share data and run asynchronous processes with different latencies, then it could take 4X or more. But then that depends on how well you model the data.

IF you look at the new multi-core Valve engine it seems like ti was a normal cycle with some additional work.
December 14, 2006 8:20:56 PM

Quote:

I think you're taking the concept too far. What they mean is that the same building blocks for a PDA will apply to the PC and MP3 /MPEG player.

The first fusion GPU will be in a laptop as integrated graphics. They won't be able to really achieve "Fusion" with a "game-level" product until 45nm when the process size will allow for the same 64 shaders on the die.

This will of course need the higher bandwidth of 2GHz DDR3 so that's a ways off yet.

I expect Barcelona to ship with an HTX "Stream" Processor, and the refresh in Jan 08 should see a socketed version using an eDRAM buffer like Xbox360.

There are already PCIe coProcs and the market just needs to increase in the HPC space and cHT will be a staple in servers before CSI even comes out. Even PCIe 2.0 won't have enough interconnect bandwidth to compete with HT3.


You imagination is fascinating but I don't think that would be true.


What don't you think would be true?
December 14, 2006 8:26:47 PM

Quote:
new system architecture


The reason for replacing the old FSB is not only about performance.

FSB requires 64 wires (excluding address bus) to connect to CPU and the northbridge while a Hypertransport only requires 22 wires (not sure, but not more than) to connect to CPu and the northbridge.

Here comes the problems:
1. Multiple FSB is not feasible especially for more than 2 links. Extremely high cost for routing the wires without crosstalk.
2. A high speed FSB will face the problem of crosstalk too.
3. All the wires must have the same length. FSB will require a higher technique, and thus higher cost to implement.
December 14, 2006 8:27:45 PM

Quote:

What don't you think would be true?


AMD is currently capacity limited.
I don't think Fusion will debut before mid-2008.

Also the DDR3 support have been postponed to 2008 or later.
December 14, 2006 8:51:51 PM

Quote:
you are forgetting amd also has a FSB
and intel has already been making boards with 2 FSB and 2 procs.
i would imagine part of the reason for getting rid of the FSB and using csi would be performance but more so it would be to link all of these new cores together.
but the fsb was never the bottleneck on the netburst processors

here is the amd roadmap showing fusion after 2008 on mobile

http://www.tgdaily.com/2006/12/14/amd_questions_multi_c...


Where is the FSB for AMD?

But if Intel thinks that quad-FSB is feasible, why they finally choose CSI?
Obviously FSB has its limitation.

FSB is the bottleneck for server class CPUs (4-way and up).
Tusla tries to reduce the FSB bottleneck by using a big pool of cache.
Intel and only Intel will use this method.
December 14, 2006 8:57:11 PM

Quote:

ok if what you say is true then please explain these benchmarks.

http://www.tomshardware.com/2006/07/14/core2_duo_knocks...

clearly intel still using its old limited bandwitdth FSB destroys amd

Well, yes if you put it in terms of Intel destroys AMD.
But that's a pretty blind perspective.
If you want to see the advantage of having an IMC VS FSB, you should just look at K8 VS K7.
K8 has 20-30% more performance than K7 clock for clock, yet the uArch is essentially the same, except for slightly better branch prediction (but a longer pipeline, which is a penalty in terms of IPC).
And SSE2/3 of course, but you can pick many tests which are not using SSE2/3 at all.
Also, to see the benefits of the IMC, you can compare the memory latency of K8 with that of Netburst.
Or the memory bandwidth of AM2 VS C2D.
But the IMC is no miracle "snake oil".
Core2 is faster than K8 is because it has a much more advanced uArchitecture.
And it compensates for the memory latency and bandwidth disadvantage thanks to a large cache and smart prefetching algorithms (which optimize the use of the large cache).
Now, i'll prevent a couple of dumb possible comebacks:
1) "dude, but AMD tried to put larger caches and it didn't help, LOLZ!!1!!"
2) "dude, but AMD has such a high memory bandwidth and still C2D PWNZ it LOLZ!!1!!"
A) yes. But that's because AMD is already enjoying nice memory performance, so a larger cache doesn't really help. The K8 has other bottlenecks, one being the cache bandwidth (both L2->L1 and L1->CPU), but most of all, it just can't crunch more data than that. Even having a higher cache bandwidth wouldn't help them at all, the K8 is pretty efficient as it is.. They need to beef up the whole pipeline.
Same goes for memory bandwidth.. actually this really is helpful or not depending on the application. Most consumer applications run on data fetched from the caches 95% of the time, and caches have way more bandwidth than main memory.
To take advantage of very high memory bandwidth you to have to deal with big dataset, or access patterns which exhibit poor spatial/temporal coherence, which cannot fit efficiently into any cache (i.e. server / data base / scientific simulations).
December 14, 2006 9:55:42 PM

Quote:
and yes amd also has an fsb in case you didnt know


Yes they do, but they haven't used it in several years...
December 14, 2006 10:03:52 PM

Quote:
and yes amd also has an fsb in case you didnt know


Yes they do, but they haven't used it in several years...

actually with the small proc cache it is a guarantee that it gets used quite often

Where does this fabled FSB go, might I ask? As in, which components of the system are they connected to?
December 14, 2006 10:25:34 PM

So now the FSB is a bunch of leads in the PCB between the IMC and the memory? That is not the case. A bus' type is defined by its controlling circuits. So your "FSB" is actually the IMC memory bus, if you want to call it that.

But if you wanna call a bunch of leads on the board a front side bus, be my guest! You'll be wrong, but you can call them whatever you want.

Edit:
Computer bus, defined:
http://www.computerhope.com/help/bus.htm
Anonymous
a b à CPUs
December 14, 2006 10:28:41 PM

I believe intel is going this way to. Lot's of people look at the cell like a design that is ahead of it's time and impractical at the moment.

I would see some core for network offloading/xml parsing/video encoding and so on, with server having more specialized core then multipurpose one.

BTW yeah, another quebecer :D 
December 14, 2006 10:41:32 PM

Quote:
thanks for letting me call it the FSB
lol maybe on an intel board we call it the emc? instead of what its really called which is the FSB


You can call it whatever you want. I don't mind.

Quote:
The front side bus as it is traditionally known may be disappearing. Originally, this bus was a central connecting point for all system devices and the CPU. However, in recent years this has been breaking down with increasing use of individual point-to-point buses.


Oh, and the IMC and Hyper-Transport are point to point busses.

http://en.wikipedia.org/wiki/Hypertransport
Section 2.1
Quote:

Front-Side Bus Replacement

The primary use for HyperTransport is to replace the front-side bus, which is currently different for every type of machine. For instance, a Pentium cannot be plugged into a PCI bus. In order to expand the system, the front-side bus must connect through adaptors for the various standard buses, like AGP or PCI. These are typically included in the respective controller functions, namely the northbridge and southbridge.

In theory, a similar computer implemented with HyperTransport is faster and more flexible. A single PCI↔HyperTransport adaptor chip will work with any HyperTransport enabled microprocessor and allow the use of PCI cards with these processors. For example, the NVIDIA nForce chipset uses HyperTransport to connect its north and south bridges.


Edit:
That was good info for me, thanks!
a b à CPUs
December 14, 2006 11:15:10 PM

Quote:
fsb has yet to be a bottle neck it never has been and isnt now. the benchmarks prove it
if the fsb was the bottleneck the tests would show as fsb bound and you would have the same scores with a c2d as you would with any other intel proc running at the same speed.

Be careful with making statements like this one, one of the reasons c2d does so well in the benchmarks as well as the (partial) reason the fsb is not a bottleneck is due to the humungous amounts of L2 cache. I'd venture that if an E6600 only had 2x512k of cache like an AM2 4600, the c2d would show quite differently in the benchies.
December 14, 2006 11:35:25 PM

Quote:
Be careful with making statements like this one, one of the reasons c2d does so well in the benchmarks as well as the (partial) reason the fsb is not a bottleneck is due to the humungous amounts of L2 cache. I'd venture that if an E6600 only had 2x512k of cache like an AM2 4600, the c2d would show quite differently in the benchies.


That was about as useful as wondering how K8 would perform without IMC+HTT.
a b à CPUs
December 14, 2006 11:46:53 PM

Quote:
fsb has yet to be a bottle neck it never has been and isnt now. the benchmarks prove it
if the fsb was the bottleneck the tests would show as fsb bound and you would have the same scores with a c2d as you would with any other intel proc running at the same speed.

Be careful with making statements like this one, one of the reasons c2d does so well in the benchmarks as well as the (partial) reason the fsb is not a bottleneck is due to the humungous amounts of L2 cache. I'd venture that if an E6600 only had 2x512k of cache like an AM2 4600, the c2d would show quite differently in the benchies.

you are making my point exactly
thanks!

What is your point? That Intel extended the life of the fsb design by beefing the L2 cache and increasing the fsb bandwidth? Given that Intel has said they are moving to an IMC and implementing CSI (which in of itself is an admission that the fsb is limited), I'm not sure if you're really making a point or stating the obvious.
December 15, 2006 12:51:25 AM

Quote:
What is your point? That Intel extended the life of the fsb design by beefing the L2 cache and increasing the fsb bandwidth? Given that Intel has said they are moving to an IMC and implementing CSI (which in of itself is an admission that the fsb is limited), I'm not sure if you're really making a point or stating the obvious.


In fact, I smell some fanboyism. :wink:
He just re-states the present situation.

But we are looking forward.
a b à CPUs
December 15, 2006 1:31:11 AM

So he's stating the obvious.

Who's "we" and what are you looking forward to? I'm not sure what any of this has to do with the article and the intent of this thread.

Anyway, back on point...I'd be interested to see if an integrated cpu/gpu could be an effective ethusiast solution. Or, a socketed gpu enthusiast solution. It could probably work if they can make a memory interface fast enough. I can totally see the benefit of an integrated co-processor solution for things like ethernet, audio DSP, and maybe even an integrated onboard XOR and RAID chip so as not to need to steal cycles from the cpu. Regardless of how AMD goesabout it, it's gonna make for some interesting products and implementations.
!