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What does "Larger cache" mean?!

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December 28, 2006 8:14:59 PM

I saw like everyone how AMD justified the increased latency of their 65nm L2, but what does a larger L2 mean to them precisely?! They're currently @ 512K on these Athlons so does it mean they will go back to 1M, will they get to 2M/core?

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December 28, 2006 8:49:56 PM

So much for the theory that AMD's nomenclature and pricing policy has absolutely any relevance whatsoever to performance...
December 28, 2006 9:40:27 PM

Can that imply additional L3 cache on actual K8 dual cores?! Barcelona (and it's derivate cores) comes out in 6-7 months, will have as they claim L3 cache and everything else K8L promises, so why think about a fial retouch to K8, especially when it's been proven that 1M L2 over 512K is almost ininfluent in performance.
Could it be that they just couldn't get the L2 memory stable with a 12-cycle latency on their new 65nm?!
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December 28, 2006 9:58:17 PM

Quote:
I saw like everyone how AMD justified the increased latency of their 65nm L2, but what does a larger L2 mean to them precisely?! They're currently @ 512K on these Athlons so does it mean they will go back to 1M, will they get to 2M/core?


This is really THE question. The 90 nm windsor, newcastle, and such processors did not show different latency between the 512x2 vs 1 meg x 2 cache sizes (single core of course 512 or 1 meg variety). Both the small and larger (1 Meg) L2 cache both had 12 cycles of latency. To justify increasing L2 latency 66% would take more than 2 meg cache per core I am guessing.... it just does not make much sense their explanation.

Firingsquad got a different explanation from AMD:
Quote:
UPDATE 12/22/06: We've received word from AMD on the surprising performance results we obtained in this article. It turns out that as a result of the half multiplier used on our 4800+ CPU, the DDR2 memory speed isn't running at the full 400MHz, while the X2 4600+ with its 12.0 multiplier is. As a result, the system memory on the X2 4600+ system ran faster than the memory on the 4800+. This is why the slower 4600+ was often able to outperform the 4800+ in our gaming tests. We will be examining this in more detail in a follow-up article.

http://firingsquad.com/hardware/amd_athlon_64_4800_65-n...

Something is very very fishy.

My question is, if it was strictly a die shrink, i.e. they didn’t diddle with the Uarch, why is there be increased latency? Theoretically, there should be a decrease, (so minute as to be unnoticeable to anyone) due to shorter pathways.

They had to have diddled with the design, or something is wrong at the node level. SOI problems at 65nm?
December 28, 2006 10:39:37 PM

You're right, even because, from the definition of latency you gave, there actually HAS to be additional cache for latency to increase; no extra cache, no (cache) reason for increased latency.
December 28, 2006 10:59:48 PM

Quote:
this is why Scott from TechReport quizzed AMD if they actually constructed a 2x1Meg cache and just disabled some to make a 2x512 KB variant of the process....

They should have added 2M+ to have such effect on latency then :roll:
however, that is too much, it's 66%, on something that appeares to be a half-shrink... it looks like thay'd have better saved the 'Santa Ana' name for Barcelona, because with all the troubles they're having, it looks like they need a miracle to get K8L competitive with Core2 :lol: 
December 29, 2006 8:49:14 AM

Quote:
this is why Scott from TechReport quizzed AMD if they actually constructed a 2x1Meg cache and just disabled some to make a 2x512 KB variant of the process....

They should have added 2M+ to have such effect on latency then :roll:
however, that is too much, it's 66%, on something that appeares to be a half-shrink... it looks like thay'd have better saved the 'Santa Ana' name for Barcelona, because with all the troubles they're having, it looks like they need a miracle to get K8L competitive with Core2 :lol: 

That is why this is THE question. Let's assume, in fact, that AMD intentionally designed 20 cycles of latency into their processor, just how much cache would that mean in order to account for 66% increase in latency and how friggen big would the cache banks need to be to cause the latency to increase that far across the die??? Their 90 nm design already showed that on a 'larger die, larger cache' latency was the same, 12 cycles be it 512 KB or 1 Meg.... so why all of a sudden do they see the need to set the latency to 20 cycles on a CPU that is printed with just 512 KB of cache?

It just does not add up.
Do you think they're trying to implement their SRAM (or ZRAM, I always make confusion between them) on die? It has extremely high density, power consumption is not a concern,... it's only problem is it's stuck @ 400MHz, however, they can make it double or quadruple data rate (in principla it's only dual channel DDR), at 20 CPU cycles of latency,... is it worth?!
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December 30, 2006 5:16:49 AM

Quote:
I would also be willing to bet money you will never see more than 1 Meg of L2 cache in any AMD process (that is cache per core). This 'explanation' is quite a story --- it does not make physical sense in terms of the processors they want to make today vs a 'future expansion' argument. This is just bull. It is sad that so many people (HW reviewers) are buying it.


And odd also that even someone like me could have seen through it... I wonder if we'll ever find out whats really going on.
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