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Intel 45nm "Penryn" Tape-Out Runs Windows

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January 10, 2007 7:37:46 AM

Quote:
Even though the processor is labeled as "A0" silicon, or first revision, the successful boot is a huge milestone and bonus for Intel. Reports of operational first-run tape-outs are few and far in-between, especially in the CPU industry.


http://www.dailytech.com/article.aspx?newsid=5657

More about : intel 45nm penryn tape runs windows

January 10, 2007 7:43:24 AM

Quote:
Even though the processor is labeled as "A0" silicon, or first revision, the successful boot is a huge milestone and bonus for Intel. Reports of operational first-run tape-outs are few and far in-between, especially in the CPU industry.


http://www.dailytech.com/article.aspx?newsid=5657

It is supposed to be announced in Q3 or Q4.
Now Intel is on tract and a little bit faster than expected :wink:
January 10, 2007 7:52:41 AM

Quote:
Even though the processor is labeled as "A0" silicon, or first revision, the successful boot is a huge milestone and bonus for Intel. Reports of operational first-run tape-outs are few and far in-between, especially in the CPU industry.


http://www.dailytech.com/article.aspx?newsid=5657

It is supposed to be announced in Q3 or Q4.
Now Intel is on tract and a little bit faster than expected :wink:

With booted first silicon -- the designers must be in heaven right now --- no major debug to just get it to work, no they can run the CPU through all the roaps and get all the bugs understood all at once, I would supsect sooner rather than later.I can't remember now, Jack....how long did you say usually from tape-out til we start seeing ES's....was it 4 months....or 6?
Related resources
January 10, 2007 8:08:56 AM

So, what JKflipflop98 said that Intel might release Penryn before K8L, might be true. If this happens, AMD will loose its credibility further. Damn, back in the K6 days.
January 10, 2007 8:12:43 AM

One can only hope.
January 10, 2007 9:39:02 AM

This is a further setback from AMD because in essence it means they are almost a generation behind Intel now, with Barcelona effectively being demoed in the same way as Penryn only a month ago.

AMD seems to have made the exact same mistake Intel made by thinking they were untouchable with the K8, as Intel did with Netburst. Unfortunately for them, they have to turn things around much faster than Intel.

AMD seems to have totally missed out a generation in technology. K8L is going to have to be one hell of an upgrade. I could see it beating the current incarnation of Core 2, but for it to beat Penryn as well? Thats asking for an awful lot.
January 10, 2007 10:51:02 AM

Quote:
Even though the processor is labeled as "A0" silicon, or first revision, the successful boot is a huge milestone and bonus for Intel. Reports of operational first-run tape-outs are few and far in-between, especially in the CPU industry.


http://www.dailytech.com/article.aspx?newsid=5657

I WANT MY MOMMY
/
:cry:  <= AMD
January 10, 2007 11:43:50 AM

Quote:
Even though the processor is labeled as "A0" silicon, or first revision, the successful boot is a huge milestone and bonus for Intel. Reports of operational first-run tape-outs are few and far in-between, especially in the CPU industry.


http://www.dailytech.com/article.aspx?newsid=5657

It is supposed to be announced in Q3 or Q4.
Now Intel is on tract and a little bit faster than expected :wink:

With booted first silicon -- the designers must be in heaven right now --- no major debug to just get it to work, no they can run the CPU through all the roaps and get all the bugs understood all at once, I would supsect sooner rather than later.They could even display Task Manager if need be I'm sure. :wink:
January 10, 2007 11:57:33 AM

:lol:  :lol:  :lol: 

Seriously though if Intel ramps 45 nm quickly, AMD will be playing catch up again. I think this is why they bought ATI. They new they needed to change the game to compete vis a vis platform solution vs processor head to head. I am waiting for intel's 45 nm with integrated IMC (is it Nehalem core? Q3?) to judge where this battle is going. All I can say AMD K8L better deliver since their credibility is fairly shaky at this point.
January 10, 2007 1:41:17 PM

I can see that the waiting game is always a gamble. I would like to upgrade my P4 but I can't justify it yet.

I really want to see K8L and Penryn.
January 10, 2007 11:52:45 PM

So can someone estimate the "gross" yield on a 300mm wafer, compared to the 65nm?
a c 480 à CPUs
a c 119 å Intel
January 11, 2007 12:35:58 AM

Quote:

After several years of lull, it is now a boxing match again.


True, but Intel is far in the lead. Even if Penryn doesn't make it out of the gate until next year Intel will still be ahead of AMD performance wise. For the moment AMD must rely on the cost savings of manufacturing 65nm processors on 300mm wafers to increase their profit margins. Or to give them more maneuvering room in pricing.

Brisbane allows AMD to play the energy efficient card though since their TDP is rated at 65w instead of 89w for Windsor cores. I'm sure there will be some Brisbane cores that will fall in the 35w TDP bucket. While Brisbane CPU consumes less power than Core 2 Duo CPU while idle, they still consume more power under load.

A shrink is always nice for a CPU, but Brisbane introduces slightly slower L2 Cache than the older Windsor core. That's bound to have some small measure of negative performance impact.

It would be nice if Penryn will be available in Q3/Q4 of this year 'cause that's when I plan to upgrade my HTPC. My E6600 will go to my HTPC while the Penryn will be dropped into my primary rig.
January 11, 2007 12:40:20 AM

Quote:
So can someone estimate the "gross" yield on a 300mm wafer, compared to the 65nm?


Two factors at play here...

A 65 nano part is almsot exactly 50% the size of the 90 namo part (assuming no changes such as more cache, or whatever)

65^2=>4225

90^2=>8100

4225/8100=>52%

Thus you will get basically trwice as many parts from 65 nano as 90 nano.

In addition, the yields usually go up as most failed cpu dies are due to defects in the wafer.

Lets assume, for sake or argument, there are 50 defects in a wafer, this will ruin 50 chips from a wafer.

If you are producing twice as many cpus from that same wafer, as a %, that same 50 defects is a smaller %.
January 11, 2007 12:42:48 AM

Quote:
This architecture revision will give AMD a great boost in IPC no doubt, compared to today's C2Ds, either catching up or surpassing (I lean to surpassing).


Integer: No
FP: Yes
Overall per clock: wash

Quote:
While Brisbane CPU consumes less power than Core 2 Duo CPU while idle, they still consume more power under load.


That'll be fixed with the new low end chips coming very very soon. E4300 is already there, E6300/E6400 will follow shortly.

For load, Conroe-L is aimed at 35W.

Quote:
A 65 nano part is almsot exactly 50% the size of the 90 namo part (assuming no changes such as more cache, or whatever)

65^2=>4225

90^2=>8100

4225/8100=>52%


In reality its nowhere near true. Dothan, a near straight shrink of Banias with small enhancements + cache, it should have a die size that is noticeably smaller than Banias. Dothan's die size is 1mm2 greater than Banias though. Overall circuit reductions are put as 70%, not 50%. Although (65/90)^2 works in theory, you won't know until the final product.

Quote:
So can someone estimate the "gross" yield on a 300mm wafer, compared to the 65nm?


You mean 90nm compared to 65nm?? :roll:

Yield is the ratio of working dies to not working dies. You probably meant number of die on the wafer for 65nm compared to 90nm.
January 11, 2007 1:59:53 AM

Hmmmm...Looks like AMD better do some quick thinking this time around.TY for the link to the info.

Dahak

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January 11, 2007 3:46:47 AM

LMFAO.Ya no doubt my friend.I could take it either way to be honest,I just enjoy rooting for the underdog.In this case it's AMD.Last 4 years it was INTEL.However their prices were quite a bit higher than AMD,and as I'm a gamer,I wanted the best for my money.Now it seems an INTEL build is in the future.

Dahak
January 11, 2007 3:52:08 AM

I wonder how long it'll be until we have picometers chips?
January 11, 2007 7:18:30 AM

Quote:
Integer: No
FP: Yes
Overall per clock: wash

I dissagree!
There will be Int IPC increase also: improved branch prediction & indirect branches, doubled instruction fetch, doubled L1/L2 data paths, etc.

Quote:
In reality its nowhere near true. Dothan, a near straight shrink of Banias with small enhancements + cache, it should have a die size that is noticeably smaller than Banias. Dothan's die size is 1mm2 greater than Banias though. Overall circuit reductions are put as 70%, not 50%. Although (65/90)^2 works in theory, you won't know until the final product.

Agreed!
Some details.
Banias has 77 million transistors and 82.8mm^2 surface.
Dothan has 140 million transistors and 83.6mm^2 surface.
The 90nm compared to 130nm in theory is taking only 48% of the surface.
In theory Dothan should have surface of 72.2mm^2.
(0.48 * 82.8 * 140 / 77 = 72.7)
Although the shrink is not ideal, it still is a 56% shrink, not a 70%:
100% * (83.6mm^2 * 77MT) / (82.8mm^2 * 140MT) = 55.53%
January 11, 2007 9:40:22 AM

The number of die on a 300mm wafer at new 45nm proccess compared to the old 65nm proccess. Will Penryn double intels production compared to Conroe? If so... 8)
January 11, 2007 10:11:09 AM

Quote:

The number of die on a 300mm wafer at new 45nm proccess compared to the old 65nm proccess. Will Penryn double intels production compared to Conroe? If so...



No

There are many factors that affect yield.

As noted above the number of errors in the raw silicon lead to that number of dead dies (excuse unintentional pun). However, the manufacturing process itself introduces errors. Not every die etched actually works at the end of the process, some simply fail. As a process matures (manufacturing experience) the yield increases, but it can start fairly low. The key to a successful production ramp is increasing not just production volume but perfecting the process so that manufacturing process losses to yield reduce, consequently increasing total yield.

Q
January 11, 2007 10:32:02 AM

>I wonder how long it will be till we have picometres chips?

We already do. Penryn is 45,000 picometres :p 
January 11, 2007 10:41:11 AM

I'm just old enough to remember the early sub-micrometre silicon that was a milestone then but i think it will be a good few years before the next 'thousand-scale' barrier is broken. The science of production shrinking is just now getting up against quantum scale effects that new ideas will be needed to overcome.

Q
January 11, 2007 10:59:04 AM

I think that pm(picometers) is SF. I think that 1nm is impossible also
January 11, 2007 11:01:18 AM

Quote:
I think that pm(picometers) is SF. I think that 1nm is impossible also


I am studing chemistry :wink:

1nm is close to atomic size already.
January 11, 2007 11:18:34 AM

Quote:
So, what JKflipflop98 said that Intel might release Penryn before K8L, might be true. If this happens, AMD will loose its credibility further. Damn, back in the K6 days.


I luv it all. the only reason I like AMD is cuz they keep Intel sharp. They've awakened the sleeping giant. I just hope that when AMD comes out with their kickarse CPU they don't go back into suspend mode as they have recently demonstrated in the past 14 months prior to the C2D on the scene era...

Woohoo!! for us!!!


Now if you'll excuse me gentlemen, I must compose myself & crawl back into my shell.
January 11, 2007 11:16:19 PM

http://www.legitreviews.com/news/3059/

Quote:
Sources inside Intel have confirmed with Legit Reviews that the company has recently run the the first A0 silicion for their upcoming 45nm Penryn processor. Penryn was able to boot Windows XP Pro inside the labs of Intel on the first try according to our sources. No word on it it would boot 64-bit Vista, but operational first-run tape-outs are few and far in-between, especially in the CPU industry. Intel will bring Penryn to the market 'later' this year, so keep an eye out for it in the second half of the year.


More confirmation.
January 12, 2007 2:19:50 AM

Quote:


In reality its nowhere near true. Dothan, a near straight shrink of Banias with small enhancements + cache, it should have a die size that is noticeably smaller than Banias. Dothan's die size is 1mm2 greater than Banias though. Overall circuit reductions are put as 70%, not 50%. Although (65/90)^2 works in theory, you won't know until the final product.

Quote:


Dothan was 2 megs of cache versus 1 meg for Banias, hence the drop in die size being less than the +/- 50%.

As a very rough estimate, a process gets you twice as many potential dies on a wafer -- assuming it is a pure optical shrink. For example, AMD's 90=>65 nano shrink close to 50% (actually about a 42% drop, they seem to have looser features at 65 nanos), due to few if any changes in the design.

Intel seems to always add cache when the shrink process.

Willamette @ 256 cache
Nothwood @ 512 cache
Prescott @ 1 meg
Cedar Mill @ 2 megs
Conroe @ 4 megs
Penryn at a (reported) 6 megs is the first break from this trend in quite a while.

The added cache is why dies have not shrunk as much as you might expect.
January 12, 2007 2:25:13 AM

Quote:
So can someone estimate the "gross" yield on a 300mm wafer, compared to the 65nm?


Two factors at play here...

A 65 nano part is almost exactly 50% the size of the 90 nano part (assuming no changes such as more cache, or whatever)

65^2=>4225

90^2=>8100

4225/8100=>52%

Thus you will get basically trwice as many candidate diesfrom 65 nano as 90 nano.

In addition, the yields usually go up as most failed cpu dies are due to defects in the wafer.

Lets assume, for sake or argument, there are 50 defects in a wafer, this will ruin 50 chips from a wafer.

If you are producing twice as many cpus from that same wafer, as a %, that same 50 defects is a smaller %.
January 12, 2007 4:47:14 AM

(I hate this general reply system, so inconvenient when replying to multiple people, which I almost always do)

Quote:
By: gOJDOI dissagree!
There will be Int IPC increase also: improved branch prediction & indirect branches, doubled instruction fetch, doubled L1/L2 data paths, etc.


Why do you disagree?? Pure architectural improvements like increasing issue width, increasing instruction fetch is known to be very minor. Improved branch prediction will also not bring significant improvements unless the branch predictor is SIGNIFICANTLY better, and its usually done when increasing pipeline stages(ie. P4/Athlon 64, P4 getting a bigger improvement). Doubled L1/L2 data paths: that will bring it par up to Intel. Though overall deficit over Core 2 Duo is ~20%, the integer deficit is much greater, in order of 30%+.

Quote:
By: gOJDOAgreed!
Some details.
Banias has 77 million transistors and 82.8mm^2 surface.
Dothan has 140 million transistors and 83.6mm^2 surface.
The 90nm compared to 130nm in theory is taking only 48% of the surface.
In theory Dothan should have surface of 72.2mm^2.
(0.48 * 82.8 * 140 / 77 = 72.7)
Although the shrink is not ideal, it still is a 56% shrink, not a 70%:
100% * (83.6mm^2 * 77MT) / (82.8mm^2 * 140MT) = 55.53%


Your calculations are off. Double the transistors does not equal double the die size. SRAM caches are significantly more compact per transistor than logic units.

Banias has nearly 50% of cache logic taking up as cache. Doubling caches mean at same process(130nm) as Banias, Dothan should have roughly 50% greater die size, and in theory, it should reduce to 75% of the die size with a smaller process(90nm)

Banias is roughly 83mm2. A theoretical 130nm version of Dothan should be at roughly 120mm2 die size.

Theoretically, 90nm Dothan should have had 60mm2 die size(Intel's 90nm SRAM is half the SRAM size of 130nm).

Dothan has nearly similar die size to Banias, slightly larger at ~84mm2.

84mm2/120mm2=70%, am I right??

Quote:
By: The Vorlon
Dothan was 2 megs of cache versus 1 meg for Banias, hence the drop in die size being less than the +/- 50%.

As a very rough estimate, a process gets you twice as many potential dies on a wafer -- assuming it is a pure optical shrink. For example, AMD's 90=>65 nano shrink close to 50% (actually about a 42% drop, they seem to have looser features at 65 nanos), due to few if any changes in the design.

Intel seems to always add cache when the shrink process.


You are basically repeating what gOJDO said on his post, and I'll repeat myself again.

Including the increased cache, Dothan's overall circuits are only 70% smaller than Banias, not 50%.
January 12, 2007 5:52:38 AM

Quote:
Your calculations are off. Double the transistors does not equal double the die size. SRAM caches are significantly more compact per transistor than logic units.

Banias has nearly 50% of cache logic taking up as cache. Doubling caches mean at same process(130nm) as Banias, Dothan should have roughly 50% greater die size, and in theory, it should reduce to 75% of the die size with a smaller process(90nm)

Banias is roughly 83mm2. A theoretical 130nm version of Dothan should be at roughly 120mm2 die size.

Theoretically, 90nm Dothan should have had 60mm2 die size(Intel's 90nm SRAM is half the SRAM size of 130nm).

Dothan has nearly similar die size to Banias, slightly larger at ~84mm2.

84mm2/120mm2=70%, am I right??

As you said the L2 cache on Banias takes 40% of the chip surface, and on Dothan it takes 56%. So, in our calculation we can't ignore the SRAM because it is half of the CPU.
If we skip the L2 cache 130nm->90nm SRAM shrink, then your math is correct:

Dothan L2 cache takes 46.8mm^2 die surface. (83.6mm^2 * .56 = 46.8 mm^2)
Dothan core takes 36.8mm^2.(83.6mm^2 - 46.8mm^2 = 36.8mm^2)

Banias L2 cache takes 33.1mm^2 die surface. (82.8mm^2 * .4 = 33.1 mm^2)
Banias core takes 49.7mm^2. (82.8mm^2 - 33.1mm^2 = 49.7mm^2)
The core shirnk is 74%. (36.8mm^2 / 49.7mm^2 = 74%)

Pictures from: http://www.mobilityguru.com/2004/05/10/intel/page3.html
January 12, 2007 6:05:12 AM

BTW, another site confirms this rumor:
Quote:
Sources inside Intel have confirmed with Legit Reviews that the company has recently run the the first A0 silicion for their upcoming 45nm Penryn processor. Penryn was able to boot Windows XP Pro inside the labs of Intel on the first try according to our sources. No word on it it would boot 64-bit Vista, but operational first-run tape-outs are few and far in-between, especially in the CPU industry. Intel will bring Penryn to the market 'later' this year, so keep an eye out for it in the second half of the year.

http://www.legitreviews.com/news/3059/

Looks like, AMD is in bigger trouble.
January 12, 2007 6:34:31 AM

Quote:
As you said the L2 cache on Banias takes 40% of the chip surface, and on Dothan it takes 56%. So, in our calculation we can't ignore the SRAM because it is half of the CPU.
If we skip the L2 cache 130nm->90nm SRAM shrink, then your math is correct:


It's true whether we include the cache or not. Caches become 70% of the size, and cores become 70%(not 74% because there are minor enhancements to the architecture) of the size. Nowhere near the theoretical (65/90)^2, and no where near Intel's SRAM size reduction of 50%.
January 12, 2007 8:18:29 AM

Quote:
As you said the L2 cache on Banias takes 40% of the chip surface, and on Dothan it takes 56%. So, in our calculation we can't ignore the SRAM because it is half of the CPU.
If we skip the L2 cache 130nm->90nm SRAM shrink, then your math is correct:


It's true whether we include the cache or not. Caches become 70% of the size, and cores become 70%(not 74% because there are minor enhancements to the architecture) of the size. Nowhere near the theoretical (65/90)^2, and no where near Intel's SRAM size reduction of 50%.Actually, you are right!!!
46.8mm^2 is the die surface taken by L2 on Dothan.
33.1mm^2 id the die surface taken by L2 on Banias.
1MB cache on Dothan takes 23.4mm^2.
23.4mm^2 / 33.1mm^2 = 0.707 or 71%
!