Is K8L with 64KB or 128KBL1 cache?

I am confused now.... :?
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More about 64kb 128kbl1 cache
  1. Quote:
    the L1D and L1I caches remain at 64KB
    It's probably talk of Unified 128 KB (Split 64 KB Each L1)
  2. Quote:
    the L1D and L1I caches remain at 64KB
    It's probably talk of Unified 128 KB (Split 64 KB Each L1)

    thx :wink:
  3. Quote:
    I am confused now.... :?


    64K Data and 64 K Instruction for a total of 128 K

    I have read somewhere than K8L will be a 64KB L1 parts. :?
  4. Of course anytime it calls for a Simple Google search, But I Knew this already, So just added it with a quote.
    I think that the K8L should have patched up Latency times, to avoid embarrassment of what the 65nm AMD had shown so far.
  5. Quote:
    I am confused now.... :?


    Each core has 64K L1, 512K L2

    The package has 2M Shared L3


    Edit:

    That's 64K for instructions and 64K for data.
  6. Wat are the Advantage & disadvantages of having a larger L1 cache?
  7. Quote:
    Wat are the Advantage & disadvantages of having a larger L1 cache?


    AMD has a relatively large L1 cache because its CPUs' caching system is exclusive.
    Intel has a relatively small L1 cache because its CPUs' caching system is inclusive.
  8. then why cant they not make a l2 or l3 cache at all and just add them to the l1?

    also will we ever see a rise in L1 cache? eg 128 + 128 (data/instuction)
    it would seem that this might be a good idea as all intel is doing is intergrating a ram socket in the cpu 0.o''

    shed some light jack oh enlightend one 8O
  9. Quote:
    Wat are the Advantage & disadvantages of having a larger L1 cache?


    AMD has a relatively large L1 cache because its CPUs' caching system is exclusive.
    Intel has a relatively small L1 cache because its CPUs' caching system is inclusive.

    Intel uses a large L2 cache because its CPUs' cacheing system is inclusive.
    and Inclusive cache is faster too.

    Then why did AMD chose an exclusive cache relation?
  10. Quote:
    Intel uses a large L2 cache because its CPUs' cacheing system is inclusive.
    and Inclusive cache is faster too.

    Then why did AMD chose an exclusive cache relation?


    It depends :wink:
    L2 cache should and must be faster in inclusive cache architecture because the frequency of loading L2 cache is significantly more than that of exclusive one.
  11. Quote:
    Wat are the Advantage & disadvantages of having a larger L1 cache?


    AMD has a relatively large L1 cache because its CPUs' caching system is exclusive.
    Intel has a relatively small L1 cache because its CPUs' caching system is inclusive.
    No, it's the other way around. :D
    AMD uses exclusive caching because it has a relatively large L1 cache.
    Intel uses inclusive caching because it has a relatively small L1 cache.
    For the same reasons, AMD has a much lower L2 <-> L1 bus bandwidth than Intel, Intel needs to swap data accross the 2 caches more often, hence it has do it faster.
    In fact, the first K7 had already a 128KB L1 cache, but used off-die inclusive L2 cache.
    On die exclusive L2 cache was introduced with the Thunderbird core.

    EDIT: mixed up the two terms, sorry :P
  12. Quote:

    No, it's the other way around. :D
    AMD uses inclusive caching because it has a relatively large L1 cache.
    Intel uses exclusive caching because it has a relatively small L1 cache.
    For the same reasons, AMD has a much lower L2 <-> L1 bus bandwidth than Intel, Intel needs to swap data accross the 2 caches more often, hence it has do it faster.
    In fact, the first K7 had already a 128KB L1 cache, but used off-die exclusive L2 cache.
    On die inclusive L2 cache was introduced with the Thunderbird core.


    Totally different from what I think :roll:
  13. AMD chose an exclusive cache arrangement back in the days of K7 thunderbird.
    The reason is that it already sported a very large L1 cache, which was only half the size of Intel's Coppermine L2 cache (which was 256KB).
    By going exclusive, AMD got a cache size advantage, because then it could have a usable 256+128= 384KB of cache.
    With Intel's inclusive approache instead, the "usable" size of the cache was in fact 256KB (this because the 32KB of L1 cache were just mirroring part of the content of the inclusive L2).
    For this reason (exclusive cache), AMD could also use a cheap and relatively slow 64 bit L2 <-> L1 bus and higher L2 cache latency, instead Intel had a massive 256bit bus and very low cache latency.
    So, back in those days, it made a lot of sense for AMD to use exclusive caches.
    But with today's L2 cache sizes (2-4MB), it doesn't make much sense IMO to use exclusive caches anymore.
    Well, maybe it does, with AMD's relatively small 512KB L2.
    My guess is that K8L L3 cache will be inclusive. (while the L2 might still be exclusive)
    This because the L3 has to serve 2 cores... so if it was exclusive, it would not mirror data which is present in *any* of the 2 caches.
    But then, if one core has some data in its L2, and the other core needs it... then the latter would have to fetch this data from the 1st core cache, or from memory... this is less efficient, than just having that data sit comfortably in the shared (and inclusive) L3.

    EDIT: i mixed up the 2 terms, sorry :D
  14. Quote:
    AMD chose an exclusive cache arrangement back in the days of K7 thunderbird.
    The reason is that it already sported a very large L1 cache, which was only half the size of Intel's Coppermine L2 cache (which was 256KB).
    By going inclusive, AMD got a cache size advantage, because then it could have a usable 256+128= 384KB of cache.
    With Intel's exclusive approache instead, the "usable" size of the cache was in fact 256KB (this because the 32KB of L1 cache were just mirroring part of the content of the exclusive L2).
    For this reason (inclusive cache), AMD could also use a cheap and relatively slow 64 bit L2 <-> L1 bus and higher L2 cache latency, instead Intel had a massive 256bit bus and very low cache latency.
    So, back in those days, it made a lot of sense for AMD to use inclusive caches.
    But with today's L2 cache sizes (2-4MB), it doesn't make much sense IMO to use inclusive caches anymore.
    Well, maybe it does, with AMD's relatively small 512KB L2.
    My guess is that K8L L3 cache will be exclusive. (while the L2 might still be inclusive)
    This because the L3 has to serve 2 cores... so if it was inclusive, it would not mirror data which is present in *any* of the 2 caches.
    But then, if one core has some data in its L2, and the other core needs it... then the latter would have to fetch this data from the 1st core cache, or from memory... this is less efficient, than just having that data sit comfortably in the shared (and exclusive) L3.


    You have mixed up inclusive cache and exclusive cache :wink:
  15. YES :lol: :lol: :lol:
    Darn you, you pointed it out while i was already correcting it :D :D
  16. Quote:
    AMD chose an exclusive cache arrangement back in the days of K7 thunderbird.
    The reason is that it already sported a very large L1 cache, which was only half the size of Intel's Coppermine L2 cache (which was 256KB).
    By going exclusive, AMD got a cache size advantage, because then it could have a usable 256+128= 384KB of cache.
    With Intel's inclusive approache instead, the "usable" size of the cache was in fact 256KB (this because the 32KB of L1 cache were just mirroring part of the content of the inclusive L2).
    For this reason (exclusive cache), AMD could also use a cheap and relatively slow 64 bit L2 <-> L1 bus and higher L2 cache latency, instead Intel had a massive 256bit bus and very low cache latency.
    So, back in those days, it made a lot of sense for AMD to use exclusive caches.
    But with today's L2 cache sizes (2-4MB), it doesn't make much sense IMO to use exclusive caches anymore.
    Well, maybe it does, with AMD's relatively small 512KB L2.
    My guess is that K8L L3 cache will be inclusive. (while the L2 might still be exclusive)
    This because the L3 has to serve 2 cores... so if it was exclusive, it would not mirror data which is present in *any* of the 2 caches.
    But then, if one core has some data in its L2, and the other core needs it... then the latter would have to fetch this data from the 1st core cache, or from memory... this is less efficient, than just having that data sit comfortably in the shared (and inclusive) L3.

    EDIT: i mixed up the 2 terms, sorry :D


    The mirroring of the cores' L2 cache into the L3 cache is resaonable :wink:

    K8L quad-core: 512KB L2 per core, shared 2MB L3 cache....
    But for dual-core: 512KB L2 per core, shared 2MB L3 cache => excess L3 cache :wink:
  17. Hmm, well, for 4 cores, 2MB of inclusive L3 cache are not that much, in fact.
    But if it was exclusive, then the processor should feature fast internal L2 cache buses, so that each core could directly retrieve data from the L2 cache of another.
    I guess such an arrangement is also possible, and potentially higher performing than the inclusive one, but definitely more complex to implement.

    EDIT: in bold.
  18. Quote:
    Hmm, well, for 4 cores, 2MB of inclusive L2 cache are not that much, in fact.
    But if it was exclusive, then the processor should feature fast internal L2 cache buses, so that each core could directly retrieve data from the L2 cache of another.
    I guess such an arrangement is also possible, and potentially higher performing than the inclusive one, but definitely more complex to implement.


    Remember the cross-bar?
    The cross-bar in K8 is supposed to be the fast inter-CPU-cache exchange bus, but it seems to be not functioning in K8 as in the test conducted by X-Bit Labs.
    An improved cross-bar is also a good expectation. :wink:
  19. I belive the crossbar in K8 is only used for each core to access the common IMC.
    Yes a crossbar could be used for L2 traffic switching in Barcelona, or even better, point to point links.
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