Core Enchancements:
128 Bit floating point:
Applies only to Agena & Kuma
New SSE4A instructions:
Advanced Bit manipulation
MWAIT & MONITOR instructions
Misaligned SSE Mode
Additional Features:
Power management state invariant time stamp counter (TSC)
increased number of TLB Page entries
1GB large paging support
Physical address space increased to 48 bits
IMC Enhancements
DDR2 Dimms in products variations:
Socket AM2+: Dual Channel unbuffered 1066 support
Socket 1207+ Dual Channel unbuffered 1066 support
Memory Controller enhancements
Write Burst & DRAM prefetching performance improovements
DRAM writes can be buffered in the memory controller before being opportunistically bursted into DRAM controler to improve DRAM interface efficiency
Read prefetcher detects stride paterns and issues prefetch requests based on confidence level
Channel Interleaving
Roadmap:
Agena FX(K8L):
Q3 2007:
2.7-2.9GHz
4x512kB L2 cache
2MB shared L3 cache
Socket 1207+, 1207 compatible
4000MHz hypertransport Bus
TDP not determined yet
65nm SOI
Agena(K8L):
Q3 2007:
2.4-2.6GHz
4x512kB L2 cache
2MB shared L3 cache
Socket AM2+, AM2 compatible
4000MHz hypertransport Bus
TDP 125W
65nm SOI
Kuma(K8L):
Q3 2007:
2.0-2.9GHz
2x512kB L2 cache
2MB shared L3 cache
Socket AM2+, AM2 compatible
4000MHz hypertransport Bus
TDP 89W, 65W
65nm SOI
Kuma EE(K8L):
Q4 2007:
2.0-?GHz
2x512kB L2 cache
2MB shared L3 cache
Socket AM2+, AM2 compatible
4000MHz hypertransport Bus
TDP 35W
65nm SOI
Rana(K8 ):
Q4 2007:
2.1-2.3GHz
2x512kB L2 cache
No shared L3 cache
Socket AM2+, AM2 compatible
2000MHz hypertransport Bus, HTT1
TDP 65W
65nm SOI
Sources:
Chilehardware
Dailytech
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