Shanghai is apparently more than just a cache-bump. AMD's documentation explicitly claims Shanghai will be the company's first 45nm processor. However, with a die shrink additional cache is one of the immediate architecture options as the smaller node allows for more transistors to fit on the chip die. Shanghai features 6MB of L3 cache.
Quote :
All other features found on Barcelona will also make an appearance on Shanghai: AMD-Virtualization (previously codenamed Presido), RDDR2, and HyperTransport 3.0. Like Barcelona, Shanghai will also tentatively ship with dual and quad-core variants. In 2008 AMD will tennatively add Secure Initialization to all its AMD-V platforms, including Shanghai.
Quote :
Shanghai will also use the Socket 1207 interface, suggesting existing motherboards will have the opportunity to upgrade to Shanghai processors -- AMD processors are typically designed to work with existing motherboards on same-socket interfaces with simple BIOS updates.
http://www.dailytech.com/AMDs+45nm [...] le5984.htm Shanghai is apparently more than just a cache-bump. AMD's documentation explicitly claims Shanghai will be the company's first 45nm processor. However, with a die shrink additional cache is one of the immediate architecture options as the smaller node allows for more transistors to fit on the chip die. Shanghai features 6MB of L3 cache.
Quote :
All other features found on Barcelona will also make an appearance on Shanghai: AMD-Virtualization (previously codenamed Presido), RDDR2, and HyperTransport 3.0. Like Barcelona, Shanghai will also tentatively ship with dual and quad-core variants. In 2008 AMD will tennatively add Secure Initialization to all its AMD-V platforms, including Shanghai.
Quote :
Shanghai will also use the Socket 1207 interface, suggesting existing motherboards will have the opportunity to upgrade to Shanghai processors -- AMD processors are typically designed to work with existing motherboards on same-socket interfaces with simple BIOS updates.
This is actually in line with what they have been saying. I figure they are prepping 1/3 of Fab 30 now to get the 45nm equipment installed.
I'm curious though if they will skip 65nm for Fab38. It seems reasonable since they have to ramp to 300mm first in at least 1/3 of the Fab to keep inventories level, but since Fab 36 is supposedly 30,000WSPM at 3.4x the same at Fab30, they shouldn't need to use 65nm at Fab 38 especially when Chartered can do both at about 3,000WSPM
ANyway, the more interesting news right now is the seeming reversal of Barcelona and Budapest. The latest model number news states 12xx chips and one 22xx will ship which are single socket AM2+/dual socket 1207+ not 4S 1207+.
That would be an interesting turn but would definitely staunch the flow for 2S systems and give enthusiasts single socket quad first.
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