AMD Licenses ZRAM Gen2

In theory AMD could put a 15 Meg L3 on its k10 for no additional cost.

zram gen2 may be fast enough for L3....

i highly doubt we will see it anytime soon.... but i have been wrong before

yay?

15 megs of zram L3 cache would consume alot less power than 3 megs of standard L3 cache

its beautiful all around... the only hinderance is the clock speed of zram...

Jack is more of the expert..... i will talk to my boy BITMEOFF...he is also a cache-ologist... see what he thinks

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could be done i would think... i yield to jack

It's interesting as IBM is gongwith eDRAM for it's next chips. Maybe AMD is hedging their bets as either one will do a great job. For now this would be good for cell phones and handhelds.

like m25 said... maybe they can quad rail it..... 400 X 4 = 15 megs of 1.6 ghz L3

There is more to it though.
Latency has an impact on performance only for sparse memory accesses.
For access to adjacent memory locations, SRAM (and even DRAM) supports burst modes where you can get a pipelined access which yields a throughput of 1 data element per clock, after locating the first element of the burst.
Since cache access is always performed per block (or cache line), the burst mode can be applied all the time and it hides most of the negative effects of (high) latency.
For example, let's say that you want transfer a block of 128 bytes from the L3 to the L2 cache, on a 128bit bus (16 bytes) and that the L3 cache has a latency of 20 clocks.
So with SRAM and a pipeline burst mode, you get the first 16 bytes after 20 clocks, but you get the rest in chunks of 16 bytes per clock.
Overall, you'd transfer your whole cache block in (1x20 + 7x1) = 27 clocks.
If your cache is running at, say, 3GHz, that's about 8.91ns.
Now let's take our ZRAM running at 400MHz, and let's suppose that the latency is only 1 clock... still, to transfer our cache block, we'd need 8 clocks, but with a clock period of 2.5ns, that would require a whopping (8x2.5= ) 20ns to transfer, more than double of what we get with high frequency SRAM.

Theoretically, you could just use a wider cache interface, or organize it in multiple banks to do some kind of interleaving, so yes you could get a higher throughput even from Z-Ram.
But since i'm not a "semiconductor guru", i have no idea about the feasibility of such a design.

I know ZRAM is much more dense and energy effective than conventional cache (If my memory is not tricking me by a large amount, I think it's something like 32MB on about 50mm^2) don't know if you can do this with eDRAM.

Ah... Such a Battlebot quote that is. 8)

I couldn't get any Unobtainium for my combat robots, so I went to Hardox 450 instead Titanium is crap

We use Kilograms over here

5.5/8 is the same as 11/16 right?

I'm fairly use to lbs simply because the combat robots I build over here match the US standards as well, so we can compete internationally. I build 30lbers (13.6kg) Featherweight Combat Robots 8)


Wow... Soooo off topic...