However, there is the latency piece --- even though it would run at the speed of the core, signal propogation, setting the bit, etc. would take more than one tick or tock... this is latency. The major portion of latency is the signal propogation to the bit cell --- this is why the general rule of thumb is the larger the cache the larger the latency. The reason?? Because the fastest you can accurately ensure you get the data from the cache will depend on the time it takes to get the last bit of data physically located the farthest from the core. So a 2 meg cache may only take up 30% of the die area, but a 4 meg cache may take up 50% of the die area. The larger 4 meg cache will have transistors and bits physically farther from the core --- hence the delay getting the signal from the bit to the core will be longer --- higher latency.
There is more to it though.
Latency has an impact on performance only for sparse memory accesses.
For access to adjacent memory locations, SRAM (and even DRAM) supports burst modes where you can get a pipelined access which yields a throughput of 1 data element per clock, after locating the first element of the burst.
Since cache access is always performed per block (or cache line), the burst mode can be applied all the time and it hides most of the negative effects of (high) latency.
For example, let's say that you want transfer a block of 128 bytes from the L3 to the L2 cache, on a 128bit bus (16 bytes) and that the L3 cache has a latency of 20 clocks.
So with SRAM and a pipeline burst mode, you get the first 16 bytes after 20 clocks, but you get the rest in chunks of 16 bytes
per clock.
Overall, you'd transfer your whole cache block in (1x20 + 7x1) = 27 clocks.
If your cache is running at, say, 3GHz, that's about 8.91ns.
Now let's take our ZRAM running at 400MHz, and let's suppose that the latency is only 1 clock... still, to transfer our cache block, we'd need 8 clocks, but with a clock period of 2.5ns, that would require a whopping (8x2.5= ) 20ns to transfer, more than double of what we get with high frequency SRAM.
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