Interesting (and disppointing) with this

[qcmadness]

http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_9487%5e10248,00.html

For single-core A64:

Die Size:
90nm: 103.1mm2
65nm: 77.2mm2

Number of Transistors
90nm: 164million
65nm: 122million

The 65nm die is even larger than 90nm die for the same number of transistor :?

 

[qcmadness]

A little bit better now:

http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_9485_13041%5E13076,00.html

For dual-core A64:

Die Size
90nm: 219 mm2
65nm: 118mm2

Number of Transistors
90nm: 164 to 243 million (depending on cache size)
65nm: 221 million

From this 221M data, I thought that Brisbane core consists of totally 2MB of L2 cache with half of the cache disabled.

 

[m25]

However, 219 to 118 mm2 is 53% of shrink, pretty impressive; I'm not surprised if Brisbane prices are constantly dropping.

 

[ajfink]

However, 219 to 118 mm2 is 53% of shrink, pretty impressive; I'm not surprised if Brisbane prices are constantly dropping.

Yeah...it seems like the 65nm shrink has served them very well in terms of volume capability.

 

[m25]

Looks like prices never stop dropping; The famous April price drops might see the E4300/6300 at about $140-130 but then the X2 3800+/ 3600+ are going to be as low as low as $80 :twisted:

 

[m25]

Maybe the decision to cut the extra 1M of L2 for ALL X2s came later and they just had to use some wafers with 2M L2, or maybe it's just a typo (even because, the reduction in die area is pretty good, maybe too good to be true and we are comparing 90nm with 2M L2 and 65 nm with 1M L2).

 

[r0ck]

Why would they specify that there are different transistor/cache models, but only specify 1 90nm die size? I think they are trying to make their shrink look good.

 

[qcmadness]

Looks like prices never stop dropping; The famous April price drops might see the E4300/6300 at about $140-130 but then the X2 3800+/ 3600+ are going to be as low as low as $80 :twisted:

I think AMD will lower the price in April or May for better shipment.

http://chip.seekingalpha.com/article/28465
Here is an article about weak demand for AMD processors in Feb.

 

[qcmadness]

This information contradicts what they gave review sites in the press kits.... interesting.... I believe this is indeed more accurate. However, it is odd that they would go to 1/2 multipliers to deliniate their product and not take advantage of the extra cache... perhaps also brushing off the added L2 latency.

I think AMD will standardize the cache size for the same series of processors.
This is indeed more easily understandable.

Without the half-multiplier, the processor portfolio will be too small. But the half-multiplier has imposed some problems in performance.

 

[qcmadness]

It doesn't make sense though .... I can see why Intel did the 2 meg 4 meg combo with all parts initially 4 meg but 2 disalbled as redundancy allows you to take a otherwise bad 4 meg die and make it a good 2 meg die... this saves money.

But to intentionally make a 2 Meg part but only use 1 meg and have the larger die.... this makes no sense... but it is on AMD's web site, this is the most accurate you can get.... so I will take it for that.

Originally I think AMD will shift the Opterons into 65 nm also. But I think I am wrong about that.

 

[qcmadness]

Why would they specify that there are different transistor/cache models, but only specify 1 90nm die size? I think they are trying to make their shrink look good.

I suspect there is only masks for Windsor cores (1MB L2 cache per core)

 

[qcmadness]

You may be, I don't know.... we will know just how healthy AMD's 65 nm process is in a few months, the mobile products are due out any time now... but given the power constraints, and the tweaks necessary to get that under control --- if those are delayed then the 65 nm process has no margin for error and logical conclusion would be they cannot yield the right bins.

What is the updated schedule for Tyler (65nm Turion x2)?