Maybe the decision to cut the extra 1M of L2 for ALL X2s came later and they just had to use some wafers with 2M L2, or maybe it's just a typo (even because, the reduction in die area is pretty good, maybe too good to be true and we are comparing 90nm with 2M L2 and 65 nm with 1M L2).
This information contradicts what they gave review sites in the press kits.... interesting.... I believe this is indeed more accurate. However, it is odd that they would go to 1/2 multipliers to deliniate their product and not take advantage of the extra cache... perhaps also brushing off the added L2 latency.
I think AMD will standardize the cache size for the same series of processors.
This is indeed more easily understandable.
Without the half-multiplier, the processor portfolio will be too small. But the half-multiplier has imposed some problems in performance. :wink:
It doesn't make sense though .... I can see why Intel did the 2 meg 4 meg combo with all parts initially 4 meg but 2 disalbled as redundancy allows you to take a otherwise bad 4 meg die and make it a good 2 meg die... this saves money.
But to intentionally make a 2 Meg part but only use 1 meg and have the larger die.... this makes no sense... but it is on AMD's web site, this is the most accurate you can get.... so I will take it for that.
Originally I think AMD will shift the Opterons into 65 nm also. But I think I am wrong about that. :wink:
You may be, I don't know.... we will know just how healthy AMD's 65 nm process is in a few months, the mobile products are due out any time now... but given the power constraints, and the tweaks necessary to get that under control --- if those are delayed then the 65 nm process has no margin for error and logical conclusion would be they cannot yield the right bins.
What is the updated schedule for Tyler (65nm Turion x2)?