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Intel's Nehalem has integrated memory controllers

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March 16, 2007 1:17:06 AM

Yes it is the Inq. http://www.theinquirer.net/default.aspx?article=38232

Sounds like Intel plans to release IMCs on EE/XE parts. It sounds logical to me because it is cheaper for them to make nonIMC parts which they can mix and match chips to make Quad cores and get higher yeilds (important for selecting mobile parts) and they can also be made more energy effiecient (also important for mobile chips). Then they can put IMCs on the high end product and charge a fortune.

I wonder how the chipsets will work out for the different products though. Could they make a chipset that will autosense the CPU type and configure itself to operate in differently or do you have to run a certain chipset??? Should be interesting. 8O
March 16, 2007 1:24:27 AM

Charlie at his best :!:

When questioned why, Intel spokespeople say "we can not comment on future products", but other sources give us a range of answers. Some cite flexibility in memory architectures, others engineering bandwith, and that guy asking for quarters outside Moscone said it was sunspots interfering with the CIA mind control orbital lasers. No two will give you the same answer though, and that we find worrying.

Toss in that there are at least four sockets coming for each application, and you have the potential for a right royal mess. Add in Jasper, a year or so later, and you have the potential for a short lived mess to be supplanted by a slightly longer life short lived mess.
March 16, 2007 1:37:13 AM

funny to see Intel stealing ideas from amd.. i can only imagine the outcry in forumz will be incredible.
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March 16, 2007 1:42:12 AM

Quote:
funny to see Intel stealing ideas from amd.. i can only imagine the outcry in forumz will be incredible.
And AMD stole x86 from Intel; both companies constantly license their technologies.
March 16, 2007 2:03:11 AM

Quote:
funny to see Intel stealing ideas from amd.. i can only imagine the outcry in forumz will be incredible.


Amd from Intel - x86
Intel from AMD - 64-bit extentions
AMD from Intel - SSE instruction sets
Intel from AMD - Integrated Memory Controllers... which AMD people have been crying out that Intel chips desperately needed for years.

Cry aloud, very loud.
March 16, 2007 2:20:27 AM

Yet strangely enough, neither complany is willing to share the letters in their names.

Intel has 100% more vowels than AMD, but still refuses to give one to AMD? How Monopolistic of 'em. :wink:
March 16, 2007 2:26:04 AM

:p 

Yes, but Advanced Micro Devices has 400% more vowels then Intel does, and the same percentage more for consanants.
March 16, 2007 2:29:07 AM

But Intel is 400% more efficient to type than Advanced Micro Devices. :o 

You're just an AMD fanboi. :roll:
March 16, 2007 3:05:37 AM

Intel stole space heater technology from G.E. when they made the P4s. :lol: 
March 16, 2007 3:34:52 AM

Quote:
Intel stole space heater technology from G.E. when they made the P4s.


LOL!! ROLFMAO!!

I'm so glad I never owned a p4! went from p3 to athlon (thoroughbred) I could never imagine such a hot monster remember those inquier articles from 04 saying prescott was going to hit over 5 ghz!!! without AMD we'd be using 300 TDP p4's! there'd be no C2D for AMD to squash again...GO L3 Cache and IMC!! Individual core voltage control!! RAWR!

how long will it take intel to get the imc right? amd will have already been building native quadcore imc'ed superbeasts for a year....unless they get bought by some gay company that chops their balls off.
March 16, 2007 3:35:51 AM

In computer industry, it is very difficult to claim "inventing something" unless you were already in the business 40 years ago. Almost all concepts can actually found their root back in the 50s and 60s, it just take 40 years for these ideas to become even remotely practical. In some cases, the ideas were practical but then became completely waste of efforts, only to become practical again due to changing requirements.
March 16, 2007 3:39:30 AM

Are they serious about the IMC being excluded from most desktop chips? If that's the case, then Intel must be going down the line AMD just started with the move to server-class sockets for FX chips and desktop-class sockets for the remiander. This is actually quite annoying, since people with AM2 boards can't get the highest-performing FX processor (then again, the 6000+ has all the features except unlocked multiplier). Still, puting the XE parts in a special socket of their own means those who want extreme performance are going to have to pay even more. The QFX board isn't cheap, and not everyone who uses the XE C2Ds buys a Striker Extreme.

Anyway, 4 concurrent sockets doesn't sound that scary or messy. There are 3 for Intel right now, of which I'm aware. There's the mobile, desktop, and server sockets. That makes sense to me. What's the fourth supposed to be?
March 16, 2007 3:47:13 AM

Intel most likely has already looked at IMCs and decided not to go with it for their own reasons (most like no need with the C2D and production costs being higher). I seriously doubt with the money Intel puts into R&D that this is terribly new to them.

Intel applies for more patents in a year than any other IC company. AMD is way way down on the list. Remember, Intel will go the route that will make them the most money and make the best bussiness sense just like any other manufacturer. I am sure they pass on developing and producing a lot of technologies just because it doesn't make good bussiness sense. This is why they are so profitable.
March 16, 2007 3:55:31 AM

Quote:
Intel stole space heater technology from G.E. when they made the P4s. :lol: 


:)  My point is an on die memory controller for microprocessors was not an AMD idea nor is it exclusive to AMD....

If the poster wants to track who followed who in what.... we can start a list...

AMD implemented Cu interconnects, Intel followed...
Intel implemented stress engineering technology (stress layers), AMD followed.
Intel implemented CoSi, AMD followed
Intel implemetned NiSi, AMD just now followed
Intel implemented eSiGe, AMD just now followed...

The list goes on.... AMD also barrowed, then reverse engineered the x86 microcode... which was Intel...

I really despise these 'who copied who' arguments, they are mundane and ridiculous.

Also, I find people who start these types of arguments, particularly on the IMC, do not really understand why the design is good in the first place, nor will acknowledge the weakness (disadvantages) of said technology.

I believe it was IBM did Cu (AMD's contribution was very limited), and Intel delayed to the next node due to some issues. For people who claimed "AMD forced Intel to do C2D", let me remind you it takes at least four years for a company to develop a modern microprocessor. Five years ago Intel were beating crap out of AMD with P4C. The reality was that P4 were designed long before heat were even an issue (mid-late 90s, when energy was cheap, oil costed 10 bucks, data centers were running RISC processors). However, it was widely believed that improving IPC were just a pipe dream (which I still believe is true, the cost of improving IPC meaningfully is simply too high in term of complexity and power comsumption), so the only foreseeable way to get performance must be high freq. There were some multi-core projects, the earliest one I can recalled was done at MIT using a lot of SPARC cores, but they were not even close to mainstream belief. By the way, for people who say C2D is a step in the right direction, all multi-core projects I knwo were looking for many simple low IPC cores running at high freq, which is also the model employed by tera-scale chip done by Intel a few months back. C2D is merely a stop loss solution that fixed some urgent problems before a real answer is provided, very much like SMT (i.e. hyperthreading).
March 16, 2007 4:13:49 AM

Jack, I really like your style. You back up everything you comment on, and call out others who spit out garbage hoping no one will catch their mistakes.

I can't wait to see the performance an on die controller gives Intel chips. That will be a sight to see. Especially with the release of DDR3. It's going to be an interesting couple of years.
March 16, 2007 4:18:09 AM

Quote:

Intel from AMD - Integrated Memory Controllers... which AMD people have been crying out that Intel chips desperately needed for years.

.


Actually, AMD Stole the integrated memory controller from the DEC Alpha EV7

(Reportedly) Intel will do a better job of stealing the IMC from DEC than AMD has (thus far) done with the full 5 link configuration originally planned for the murdered EV8 design that Intel and HP commited Alphacide upon to bring us the glorious Itanium chip...

Just a small note in the interest oof historical accuracy :) 
March 16, 2007 5:51:41 AM

Quote:
Intel stole space heater technology from G.E. when they made the P4s. :lol: 



Doood nice ATTACK!!!!!!!!Yeah your right "but Who has watched "THE CORE" starring Hillary swank......Intel Engineers where inspired in that movie .... so i wonder if they coined that name in that movie
March 16, 2007 7:53:44 AM

Quote:
Yes it is the Inq. http://www.theinquirer.net/default.aspx?article=38232

Sounds like Intel plans to release IMCs on EE/XE parts. It sounds logical to me because it is cheaper for them to make nonIMC parts which they can mix and match chips to make Quad cores and get higher yeilds (important for selecting mobile parts) and they can also be made more energy effiecient (also important for mobile chips). Then they can put IMCs on the high end product and charge a fortune.

I wonder how the chipsets will work out for the different products though. Could they make a chipset that will autosense the CPU type and configure itself to operate in differently or do you have to run a certain chipset??? Should be interesting. 8O


The efficiency of incorporating memory controller depends on the architecture. So for an IMC-expected system, when you add the manual memory controller, the system will be slower than a natively EMC system. :wink:
March 16, 2007 9:04:33 AM

Quote:
Yes it is the Inq. http://www.theinquirer.net/default.aspx?article=38232

Sounds like Intel plans to release IMCs on EE/XE parts. It sounds logical to me because it is cheaper for them to make nonIMC parts which they can mix and match chips to make Quad cores and get higher yeilds (important for selecting mobile parts) and they can also be made more energy effiecient (also important for mobile chips). Then they can put IMCs on the high end product and charge a fortune.

I wonder how the chipsets will work out for the different products though. Could they make a chipset that will autosense the CPU type and configure itself to operate in differently or do you have to run a certain chipset??? Should be interesting. 8O

according to this Nehalem memory controller intel will integrated this last only in server cpu witch will have socket LGA 1366 . other desktop and low end cpu will not have the memory controler and here intel can use the good old 775 socket
March 16, 2007 9:06:30 AM

Quote:
according to this Nehalem memory controller intel will integrated this last only in server cpu witch will have socket LGA 1366 . other desktop and low end cpu will not have the memory controler and here intel can use the good old 775 socket


No, Socket H (715 contacts) will be introduced in 2008 to replace Socket 775.
March 16, 2007 9:10:47 AM

Quote:
according to this Nehalem memory controller intel will integrated this last only in server cpu witch will have socket LGA 1366 . other desktop and low end cpu will not have the memory controler and here intel can use the good old 775 socket


No, Socket H (715 contacts) will be introduced in 2008 to replace Socket 775.

if there is no memory controler i can't see clear reason why intel will move to new socket
March 16, 2007 9:15:34 AM

Quote:
if there is no memory controler i can't see clear reason why intel will move to new socket


Different CPU-Northbridge interconnect (CSI vs FSB).
March 16, 2007 9:19:45 AM

can u please point me to some additinal info about this new CPU-Northbridge interconnect :) 
March 16, 2007 9:25:08 AM

Quote:
can u please point me to some additinal info about this new CPU-Northbridge interconnect :) 


The Common System Interface (CSI), is a high bandwidth Hypertransport-like bus which can be used for CPU-Northbridge interconnect or CPU-CPU interconnect. :wink:
March 16, 2007 11:55:26 AM

You spoke of disadvantages and inherent weaknesses in the integrated memory controller. Could you expand on that please?
Thanks :) 
a c 99 à CPUs
March 16, 2007 12:46:54 PM

Quote:
Are they serious about the IMC being excluded from most desktop chips? If that's the case, then Intel must be going down the line AMD just started with the move to server-class sockets for FX chips and desktop-class sockets for the remiander. This is actually quite annoying, since people with AM2 boards can't get the highest-performing FX processor (then again, the 6000+ has all the features except unlocked multiplier). Still, puting the XE parts in a special socket of their own means those who want extreme performance are going to have to pay even more. The QFX board isn't cheap, and not everyone who uses the XE C2Ds buys a Striker Extreme.


The "people who want more performance are going to have to pay more for it" is a feature, not a bug. Anyway, I bet that the best non-Extreme Edition CPU will be only a few percent slower than the XE chips if the past few years have been any indication:

1. Pentium 4 XE (Gallatin) 3.2 vs. Pentium 4 3.2C: little faster
2. Pentium 4 XE (Gallatin) 3.4 vs. Pentium 4 3.4C: little faster
3. Pentium 4 XE (Gallatin) 3.46 vs. Pentium 4 (Prescott) 560: slower
4. Pentium 4 XE (Prescott) 3.73 vs. Pentium 4 (Prescott) 570: slower
5. Pentium D 840EE vs. Pentium D 840: similar
6. Pentium D 955EE vs. Pentium D 950: little faster
7. Pentium D 965EE vs. Pentium D 960: little faster
8. Core 2 Duo X6800 vs. Core 2 Duo E6700: somewhat faster
9. Core 2 Quadro X6700 vs. Core 2 Quadro E6600: somewhat faster


Quote:
Anyway, 4 concurrent sockets doesn't sound that scary or messy. There are 3 for Intel right now, of which I'm aware. There's the mobile, desktop, and server sockets. That makes sense to me. What's the fourth supposed to be?


There are actually four sockets used by Intel: socket 775 for the desktop, socket 771 for Xeon DP/MP setups, socket 479 for mobile chips, and PAC611 for the Itanium 2s. However, Itaniums are rare, so three are the common sockets. AMD currently has three sockets as well, socket AM2 for all desktop CPUs, socket S1 for laptop CPUs, and socket 1207 for servers and the QuadFX. Technically there is 1207 and 1207FX, but since they're the same physical socket and socket 1207 Opterons work in the 1207FX board, I'll consider them the same socket.
March 16, 2007 1:26:43 PM

Quote:

Intel from AMD - Integrated Memory Controllers... which AMD people have been crying out that Intel chips desperately needed for years.

.


Actually, AMD Stole the integrated memory controller from the DEC Alpha EV7

(Reportedly) Intel will do a better job of stealing the IMC from DEC than AMD has (thus far) done with the full 5 link configuration originally planned for the murdered EV8 design that Intel and HP commited Alphacide upon to bring us the glorious Itanium chip...

Just a small note in the interest oof historical accuracy :) 

HP didn't murder the DEC Alpha, Compaq did. The DEC Alpha was killed prior to HP acquiring Compaq. Compaq had acquired DEC, claimed that they would continue to produce DEC processors and then stuck a knife in it (no, I'm not bitter... :cry:  ).
March 16, 2007 2:10:18 PM

I guess CxE will be split up in two parts:
a, regular usage - no IMC
b, 2S usage -> Vxx -> w/ IMC
Ya, I know, noone needs V8 or even less QuadFX, but 2S desktop is on the market now and Intel doesnt wanna look dumb not having a comparable product.

But there are no signs of an additional socket.
March 17, 2007 4:10:17 AM

Quote:
You spoke of disadvantages and inherent weaknesses in the integrated memory controller. Could you expand on that please?
Thanks :) 


There are a few major advantages and a couple of disadvantages for putting the memory controller on die.

The advantages are pretty clear, and you read about them all the time. The on die memory contoller brings the memory 'closer' to the core, in that it allows for the higher bandwidth and lower latency over a memory controller on the northbridge. This most people understand easily. Secondar to that is the fact that it allows for less cache with less of a performance hit, and this is really the crux of the argument.

The CPU chugs along, requesting data from high speed cache, when the data is not there it must fetch the data into cache from main memory, this is a cache miss. Larger caches with prefetch logic will prefetch the data to cache while the CPU is working on other data/instructions. The larger the cache and the better the prefetchers, the higher likelihood that instructions/data will be found in cache, conversely the smaller the cache the higher the miss rate.

If you read up on cache design and affectcs, the miss rate is almost geometric with respect to cache size, such that by the time you reach 4 megs, the miss rate is less than a few percent of the total requests from cache.

However, if one increases the speed to main memory the penalty for a miss is not as large as for slower memory access. What AMD does is use this 'higher speed' to their advantage, and implement smaller caches.... the result is AMD chips with the IMC are more senstive to higher speed and lower latency memory. However, it gets the die size down as smaller caches with the IMC yield smaller die overall.

I have read in places that the total transistor count for the IMC is about 15% of the total transistor count for the die, this is quite large, but if you save 30% of the die size with smaller cache it is a win.

Intel, having the memory controller off die, suffers from both bandwidth and latency as now work is done to organize and push data from memory to CPU through a mediator. On off die memory controller will always come in second to an on die memory controller for both latency and BW. How to remedy?? Well, large cache buffers this out so to speak, for the exact same reasons above. I won't go into much more detail but to say the data speaks for itself.... Core 2 Duo shows 30% less memory BW and roughly equivalent memory latency to AMD's X2 line using syntethics designed to test and stress memory access --- but in real apps, C2D wins --- how can this be if the BW is slower, a few reasons --- a) the total theoretical BW is no where near max used in DT usage and b) the large cache decreases the bus traffic on critical data by having it close to the core to begin with.

Summary, advantages --- high speed connection enables smaller die and smaller die size.

Ok, disadvantages --- the IMC is why AMD cannot do a MCP design... well, they could if they wanted to, but it would either a) perform worst than Intel's MCP design because one core would always slave off the other or b) they would need a completely new socket and force a NUMA on a single socket system. Intel is completely correct when they say the MCP design has the time to market and yield advantage, and if it were economically viable I guarantee AMD would be doing the same thing.

Second disadvantage --- new memory technologies require rework of the IMC, which means new masks and new design efforts for the entire die.... i.e. it sucks to screw with your design that already works just because you want to support newer memory. Luckily for AMD the DDR3 and DDR2 are close enough, they can design in cross compatibility this round... but the next late and great memory technology that is not DDR2 or 3 will not be so kind (or it might, depends on how compatible the memory makers want to keep it).

Summary disadvantages -- forces redesign of your core product if new technologies become available (common Intel argument), prevents MCP appraoch and forces monolithic design.

Jack

DUDE URE GETTING A DELL!!!

just dont get busted for smoking the chronic
March 17, 2007 4:50:32 AM

Thanks. Its a lot to ponder and do research over. Thanks again. :) 
a c 99 à CPUs
March 17, 2007 12:02:10 PM

Ideally, yes, you'd want the data in L2 as it's a lot faster than getting it from RAM. But putting bigger and bigger caches on-die makes the dies bigger and drives prices up. And as Jack said, cache misses tend to level off after a certain die size. So you could put 16MB L2 on a Core 2 Duo die, but that would make the chip very expensive and not a whole lot faster.
March 17, 2007 1:13:57 PM

Quote:
Actually, AMD Stole the integrated memory controller from the DEC Alpha EV7


Most 8-bit CPUs had 'integrated memory controllers' (i.e. they could be directly wired to RAM and ROM chips), so I doubt that DEC came up with the idea for the Alpha.

I'm not sure whether the Intel 4004 counts, as according to Wikipedia it could connect directly to Intel's special memory chips but needed external support for standard RAMs.
March 17, 2007 2:48:56 PM

Quote:
Actually, this is true .... the root of the AMD IMC came from DEC. I just wanted to point out that putting a memory contoller on die is not novel -- it has been proposed and done long before AMD even considered it.


Not only IMC, but Hypertransport is from EV7 bus :wink:
a c 99 à CPUs
March 17, 2007 3:33:27 PM

Not surprising since a lot of DEC engineers went and joined AMD after the Alpha was axed. Just goes to show that it's hard to kill good ideas.
March 17, 2007 3:43:27 PM

Great explanation! Thinking about it, we have seen all your illustrated characteristics on K8s IMC; from reduced max. L2 (1024 to 512), to 939-AM2 switching which was only done to allow the use of DDR2.
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