http://www.tgdaily.com/content/view/31408/135/
http://www.chipzilla.com/default.aspx?article=38566
Intel is continuing to push the Penryn line with smaller die (65nm>45nm), bigger cache (4MB > 6MB Dual Core, 8MB > 12MB Quad Core), SSE4 and new S3 ops to intergrate with increased cache associativity (16 way >24 way). Clock speeds, for now, appear to be only slightly increased, ie. topping at 3.2-3.3 Ghz. However, TDP appears to have dropped even more, though Intel is modestly claiming that they will "hold" it to the same TDP as the 65nm process. Additionally, FSB will further increase from 1333 Mhz > 1600 Mhz.
With Nehalem (expected late Q1-early Q2 2008), Intel is introducing their own version of an intergrated memory controller (IMC) , known as the "Nehalem System Controller", which aims to introduce "burst"-style point-to-point cpu requests and receipts. Additionally, Nehalem will offer up to 8 cores, and will see the return of "hyper-threading" (virtual cores), along with an updated SMTP (simultaneous multi-threaded processing) instruction and control scheme. Initially released at 45nm fab, Nehalem will be further shrunk down to 32nm, in late 2008.
Does anyone want to guess whether AMD will be able to stay competive with the break-neck pace that Intel is going? 'Cause it certainly appears like intel is trying to crush AMD into the dust..
http://www.chipzilla.com/default.aspx?article=38566
Intel is continuing to push the Penryn line with smaller die (65nm>45nm), bigger cache (4MB > 6MB Dual Core, 8MB > 12MB Quad Core), SSE4 and new S3 ops to intergrate with increased cache associativity (16 way >24 way). Clock speeds, for now, appear to be only slightly increased, ie. topping at 3.2-3.3 Ghz. However, TDP appears to have dropped even more, though Intel is modestly claiming that they will "hold" it to the same TDP as the 65nm process. Additionally, FSB will further increase from 1333 Mhz > 1600 Mhz.
With Nehalem (expected late Q1-early Q2 2008), Intel is introducing their own version of an intergrated memory controller (IMC) , known as the "Nehalem System Controller", which aims to introduce "burst"-style point-to-point cpu requests and receipts. Additionally, Nehalem will offer up to 8 cores, and will see the return of "hyper-threading" (virtual cores), along with an updated SMTP (simultaneous multi-threaded processing) instruction and control scheme. Initially released at 45nm fab, Nehalem will be further shrunk down to 32nm, in late 2008.
Does anyone want to guess whether AMD will be able to stay competive with the break-neck pace that Intel is going? 'Cause it certainly appears like intel is trying to crush AMD into the dust..