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Penryn and Nehalem; Can AMD catch up? - Page 2

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April 2, 2007 2:45:16 AM

Quote:

My whole point is I believe in 'Innocent Until Proven Guilty'.... Some people on this forum, have already tried and convicted AMD for lieing about k10 performance, when we haven't even seen benchmarks showing that it underperform their claims.... It is ok to be skeptical, but some people are being liable and slanderous, by accusing AMD of being liers....

That is completely hippocritical....


No-where have I claimed that AMD is lying. However, C2D is proven and Barcelona is not (at least to any public sources). I can CLAIM my Honda Civic has a top-speed of 120MPH, but that doesn't mean it actually does. It's one thing to knowingly lie about something, but it's not much better to make claims and figures without proof and verification.

In the case of what AMD is claiming in how the Barcelona performs, I will withhold judgement, and therefore value, until there is reliable, independent verification of the CPU's performance in a variety of systems and programs. Because that's the real-life, bottom-line proof. Anything else is pure speculation, and has no real bearing. Until the CPU is put in a motherboard and running programs, it's simply an interesting idea.

I am not an Intel or AMD fan. I am a PERFORMANCE fan. I cheered just as much for AMD 3-4 years ago with their K7 designs. My 'loyalty' is earned by whoever has the better processor for my wants and needs, for the price I'm willing to pay. If you base the buying of a CPU on anything else, you're in the wrong place. And no matter WHICH 'one side' you choose, you'll eventually wind up screwing yourself.
April 2, 2007 7:51:27 AM

Quote:
Not only is AMD meeting Intel head-to-head; C2D E6600 = X2 6000+ they are doing this with a 4 year old architecture. Fact is Intel has sold crap for the last 4 years and thats what they will be selling for 4 years more once AMD releases in 3 months. You forget Intel is a master at marketing more than electronics, like IBM.


As punishment for being so stupid you should only buy AMD for the next four years. :lol: 

Intel released Quad core processors for desktops last year. AMD will be close to a year behind in releasing their first Quad core. AMD has nothing to compete with Intel's top of the line processors and won't until Fall 2007/Spring 2008. Intel has not even tapped into the headroom on their current processors and are just now starting to dink with the FSB to refresh their product line up. Anyone who thinks Intel couldn't release a C2D tommorrow with a 1600FSB or at 3.5 GHZ has never owned one. The reason they don't is because their is no competition and they can wait until 45nm and do it with less heat and pwr.

No I am not a fanboy, I am just a crusader against blantant stupidity.

Obviously you don't know your stuff cause Intel released a dual package dual core not a quad core. Big difference especially in caching capabilities; just more to suprise you when Barcelona launches. I'd guess to say that over 95% of C2Ds sold are E6600 or lower also. AMD is doing just fine, they are secretive because they need to be. As the underdog they have to hold some details back untill launch. Just look at the video card market if you can't figure out why.
April 2, 2007 8:25:02 AM

Quote:
Not only is AMD meeting Intel head-to-head; C2D E6600 = X2 6000+ they are doing this with a 4 year old architecture. Fact is Intel has sold crap for the last 4 years and thats what they will be selling for 4 years more once AMD releases in 3 months. You forget Intel is a master at marketing more than electronics, like IBM.


As punishment for being so stupid you should only buy AMD for the next four years. :lol: 

Intel released Quad core processors for desktops last year. AMD will be close to a year behind in releasing their first Quad core. AMD has nothing to compete with Intel's top of the line processors and won't until Fall 2007/Spring 2008. Intel has not even tapped into the headroom on their current processors and are just now starting to dink with the FSB to refresh their product line up. Anyone who thinks Intel couldn't release a C2D tommorrow with a 1600FSB or at 3.5 GHZ has never owned one. The reason they don't is because their is no competition and they can wait until 45nm and do it with less heat and pwr.

No I am not a fanboy, I am just a crusader against blantant stupidity.

Obviously you don't know your stuff cause Intel released a dual package dual core not a quad core. Big difference especially in caching capabilities; just more to suprise you when Barcelona launches. I'd guess to say that over 95% of C2Ds sold are E6600 or lower also. AMD is doing just fine, they are secretive because they need to be. As the underdog they have to hold some details back untill launch. Just look at the video card market if you can't figure out why.

More obviously, YOU don't know what your talking about. Intels Quad-Cores HAVE 4 cores! They are simply on 2-dies, not one. So, IF Barcelona is released quickly enough, they will have the first single die 4 core CPU. It's not dual package, that what the FX-7x (4x4) processor sets are.

HUGE DIFFERENCE! HHHUUUUGGGEE!

As for cache latency.. neither you, nor me, nor anybody else outside of AMD have a clue as to how good AMD solutions are. That's blatant FUD!

Get a clue and do more research before you decide to repudiate some one else..
April 2, 2007 8:33:52 AM

Quote:
I'd guess to say that over 95% of C2Ds sold are E6600 or lower also.


Would it be worth noting that virtually 100% of those CPU's are capable of exceeding X6800 performance... on air cooling, most of which could by 10% and more...
April 2, 2007 9:37:51 AM

Quote:
I'd guess to say that over 95% of C2Ds sold are E6600 or lower also.


Would it be worth noting that virtually 100% of those CPU's are capable of exceeding X6800 performance... on air cooling, most of which could by 10% and more...

E4300 @ 3.6ghz on air cooling here :D 
April 2, 2007 9:45:12 AM

I will agree that Intel will probably beat AMD in standard desktop apps/single threaded apps, but in the server space I think there will be some suprises.
Currently in server based apps a quad socket dual core opteron beat a quad core dual socket C2D (or woodcrest)

see the following for an SAP based benchmark (The SAPs column is what you need to compare)

http://www50.sap.com/benchmarkdata/sd2tier.asp

To extract some info from the same manufacturer to try and keep things fair
IBM System x3650, 2 processors / 8 cores / 8 threads, Quad-Core Intel Xeon Processor X5355 2.66 GHz, 64 KB L1 cache per core and 4 MB L2 cache per 2 cores Score : 9270

IBM AMD Opteron LS41 for IBM BladeCenter, 4 processors / 8 cores / 8 threads, AMD Opteron Processor Model 8220SE 2.8 GHz, 128 KB L1 cache and 1 MB L2 cache per core Score 10120

Now the problem with the current C2D architecture is that it only scales to two sockets. Whereas the Opteron can currently scale to 8 sockets (albeit not that well, but Barcelona should scale much better).
This will east heavily into Intels Itanium line. I personally believe that the C2D line is being deliberatly held back as not to steal Itaniums thunder.
April 2, 2007 9:49:32 AM

Quote:
I will agree that Intel will probably beat AMD in standard desktop apps/single threaded apps, but in the server space I think there will be some suprises.
Currently in server based apps a quad socket dual core opteron beat a quad core dual socket C2D (or woodcrest)

see the following for an SAP based benchmark (The SAPs column is what you need to compare)

http://www50.sap.com/benchmarkdata/sd2tier.asp

To extract some info from the same manufacturer to try and keep things fair
IBM System x3650, 2 processors / 8 cores / 8 threads, Quad-Core Intel Xeon Processor X5355 2.66 GHz, 64 KB L1 cache per core and 4 MB L2 cache per 2 cores Score : 9270

IBM AMD Opteron LS41 for IBM BladeCenter, 4 processors / 8 cores / 8 threads, AMD Opteron Processor Model 8220SE 2.8 GHz, 128 KB L1 cache and 1 MB L2 cache per core Score 10120

Now the problem with the current C2D architecture is that it only scales to two sockets. Whereas the Opteron can currently scale to 8 sockets (albeit not that well, but Barcelona should scale much better).
This will east heavily into Intels Itanium line. I personally believe that the C2D line is being deliberatly held back as not to steal Itaniums thunder.


Well, then indeed we need the chip manu's to do better procuction, nothing a little healthy competition can not cure, or at least speed up del9very of future solutions to the end user....
April 2, 2007 9:53:11 AM

Quote:
I personally believe that the C2D line is being deliberatly held back as not to steal Itaniums thunder.


What you "personally believe" is wrong. Itanium is a TOTALLY different uArch to the C2D and is intended for a different purpose to the C2D.

So Intel holding back the C2D because it would "steal" market from Itanium is just a silly idea really.
April 2, 2007 10:02:06 AM

:twisted: We really know that performance is held back just to tempt AMD to keep trying to engineer a better CPU for the spirit and profitability of competition to keep PC chips hot and prices rolling...
Which is why Intel is holding back higher clock speeds and 45nm chips already being binned and sorted waiting for counterattack to Barc preview release to unleash them just as launch date arrives spoiling the moment for AMD. :roll:
April 2, 2007 10:02:49 AM

I should have said C2D architecture, i.e. Xeon which is what the affore mentioned benchmarks relate to.
Outside of HPC computing the Itanium is mainly sold for back office applications, e.g. ERP, CRM, SRM applications. Where scalability/consolidation is required.
However in the small to medium size market buying a massive HP superdome with 64 sockets is not really an option, an 8 way would do the job. Now if you look at the price performance differences between an 8 socket Opteron system and an 8 way Itanium, the Itanium just cannot compete, the itanium only comes into its own after 16 Sockets.

To say that Xeon and Itanium are intended for different purposes is rather short sighted. As intel are desperatly trying to sell itanium into any market possible
April 2, 2007 10:13:38 AM

Quote:
Not only is AMD meeting Intel head-to-head; C2D E6600 = X2 6000+ they are doing this with a 4 year old architecture. Fact is Intel has sold crap for the last 4 years and thats what they will be selling for 4 years more once AMD releases in 3 months. You forget Intel is a master at marketing more than electronics, like IBM.


OK, it's time to lay off the crack.. :roll:

Seriously, any OBJECTIVE (meaning UNBIASED) person knows that the C2D chipset is the better ,price and performance-wise, for the mid to high end CPU market (AMD does have better low and entry-level chips). The C2D is better in FP, Integer, Power-usage, TDP, and instruction latency than equally clocked X2's (including the new Brisbanes). And don't forget, there's also the E6700,Q6600,X6800, and the QX6700. Also, a plain vanilla E6600 can easily (greater than 95% chance) be overclocked to 3.2 Ghz on air. How far can the 6000+ be OC'ed?

Facts are facts.. AMD got their @sses handed to them this round. I am merely wondering if they have the cajones to pull their collective heads out and get back in the game. Deep down, I don't want AMD to get their teeth kicked in, but they need to actually do something. This habit they're getting into of sticking their fingers in their ears and humming real loud, and occassionaly shouting "INTEL SUX!" , isn't doing anything..

Not sure what your reply has to do with the fact that a Athlon X2 6000+ offers the same performance as a E6600 for the same price. OCing isn't always a lock and isn't always cheap when HQ parts need to be purchased. I read THG do you? http://www.tomshardware.com/2007/02/20/does-amds-athlon... New stepping hits 3.30 all day if thats what your looking for.

That's because intel is letting them, If intel wanted they could release minimum of 3ghz parts. That would be stupid, plus they know AMD can't make enough 6000+'s or sell enough of them to make any decent money.
No point going into a price war with yourself is there.
April 2, 2007 10:39:57 AM

Quote:
I'd guess to say that over 95% of C2Ds sold are E6600 or lower also.


Would it be worth noting that virtually 100% of those CPU's are capable of exceeding X6800 performance... on air cooling, most of which could by 10% and more...

That's not saying much really .. the cost is in the memory.
April 2, 2007 11:01:49 AM

Quote:


Obviously you don't know your stuff cause Intel released a dual package dual core not a quad core. Big difference especially in caching capabilities; just more to suprise you when Barcelona launches. I'd guess to say that over 95% of C2Ds sold are E6600 or lower also. AMD is doing just fine, they are secretive because they need to be. As the underdog they have to hold some details back untill launch. Just look at the video card market if you can't figure out why.


More obviously, YOU don't know what your talking about. Intels Quad-Cores HAVE 4 cores! They are simply on 2-dies, not one. So, IF Barcelona is released quickly enough, they will have the first single die 4 core CPU. It's not dual package, that what the FX-7x (4x4) processor sets are.

HUGE DIFFERENCE! HHHUUUUGGGEE!

As for cache latency.. neither you, nor me, nor anybody else outside of AMD have a clue as to how good AMD solutions are. That's blatant FUD!

Get a clue and do more research before you decide to repudiate some one else..

Slow down and read more carefully next time. Obviously the Core2Quad has four cores but it is not a "True" quad core processor it has one package containing two dies, each die containing two cores. Traditionally a die is considered one CPU. I didn't mention cache latency; I mentioned CPU caching capabilities. The benefit of a "True" quad core cpu, unlike the Core2Quad which the two DC dies are not connected to each other, is that EACH CORE is connected to each other directly and can share cache memory directly which increases performance dramatically.
April 2, 2007 11:07:25 AM

True quadcore. Hnn. Right. So suddenly, every Q series is a fake.
April 2, 2007 11:22:01 AM

an now AMD has decided to use some of that Intels GlueAll for themselves...
April 2, 2007 11:25:43 AM

Quote:
That's not saying much really .. the cost is in the memory.

Right, the cost is in the memory which happens to be the same DDR2-800 an AMD needs to run efficiently... :? Not really a whole lot of difference there especially considering most people get at least DDR2-667 for C2D.
April 2, 2007 11:25:57 AM

Quote:
True quadcore. Hnn. Right. So suddenly, every Q series is a fake.


haha yeah i love this argument. That's like saying "true 200mph". The quad cores perform. Okay it's 2 duals stuck together/.

It's irrelevant anyway, since AMD don't have any quad core solution available to buy. They'd do the same if they could.
April 2, 2007 11:42:09 AM

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Penryn and Nahalem Can Intel catch up to Fusion, Bulldozer, 4X4+

Fusion is still on the drawing board and 4x4... well, still sucks.
April 2, 2007 12:14:17 PM

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That's not saying much really .. the cost is in the memory.

Right, the cost is in the memory which happens to be the same DDR2-800 an AMD needs to run efficiently... :? Not really a whole lot of difference there especially considering most people get at least DDR2-667 for C2D.
AMD X2 benefits from low latency not high speed / bandwidth. Hypertransport bus allow synchronous memory operation at all times.
April 2, 2007 12:20:24 PM

Quote:
True quadcore. Hnn. Right. So suddenly, every Q series is a fake.


haha yeah i love this argument. That's like saying "true 200mph". The quad cores perform. Okay it's 2 duals stuck together/.

It's irrelevant anyway, since AMD don't have any quad core solution available to buy. They'd do the same if they could.

No it's like saying in a "True" quad core ALL four of the cores talk to each other inside the die and share resources. And with the C2Q they don't, Intel just put the two sockets usually on the mobo on the chip; BIG DIFFERENCE. It's like the differrence between PCI-E and NO PCI-E, hardly trivial. I'll try to make it even clearer: with Barcelona one core can use all 12MB of cache, two cores can use 6MB each, and four cores can use 3MB each; depending on workload.
April 2, 2007 12:24:52 PM

I guess I should have been clearer but I figured you'd be smart enough to know to use low latency parts on your own. In any case there isn't a whole lot of difference going from DDR2-667(675 for some Corsair kits) low latency to DDR2-800 low latency. At most there is about a $20 difference between the bottom end 2x1GB kits of each. Let's be honest now, $20 will barely even get you a plain disk drive so it isn't like there is a ton more expense here. Even if you wanted to compare low latency DDR2-800 to normal DDR2-667 you wont find more than about a $40 difference. So you could get a game with your Intel system that you couldn't afford with an AMD, and this is assuming prices are equal for everything else.
April 2, 2007 12:42:18 PM

Quote:
I guess I should have been clearer but I figured you'd be smart enough to know to use low latency parts on your own. In any case there isn't a whole lot of difference going from DDR2-667(675 for some Corsair kits) low latency to DDR2-800 low latency. At most there is about a $20 difference between the bottom end 2x1GB kits of each. Let's be honest now, $20 will barely even get you a plain disk drive so it isn't like there is a ton more expense here. Even if you wanted to compare low latency DDR2-800 to normal DDR2-667 you wont find more than about a $40 difference. So you could get a game with your Intel system that you couldn't afford with an AMD, and this is assuming prices are equal for everything else.

Quote:
capable of exceeding X6800 performance... on air

AMD X2 gets NO improvement above DDR2-667; whereas todo the above (exceed X6800) with an E4300 you need above DDR2-800 like DDR2-1066, not cheap. Or else your gimped ..
April 2, 2007 12:57:43 PM

Quote:

AMD X2 gets NO improvement above DDR2-667; whereas todo the above (exceed X6800) with an E4300 you need above DDR2-800 like DDR2-1066, not cheap. Or else your gimped ..


What the hell are you smoking? DDR2-667 allows me to run my E4300 at 3.6ghz (400FSB) using a 1:1 ratio.
April 2, 2007 1:10:06 PM

Quote:

AMD X2 gets NO improvement above DDR2-667; whereas todo the above (exceed X6800) with an E4300 you need above DDR2-800 like DDR2-1066, not cheap. Or else your gimped ..


What the hell are you smoking? DDR2-667 allows me to run my E4300 at 3.6ghz (400FSB) using a 1:1 ratio.

1:1 hmm thats DDR2-800 speeds and most of the benchies I saw on THG showing it near a X6800 used higher than that. Ur going to meltdown at 3.6Ghz; whats your load temps in Pr95 torture? jc
April 2, 2007 1:35:29 PM

No, not until they release a new architecture. Problem is that AMD hasnt announced anything that even comes close to something like a new architecture.
April 3, 2007 5:15:40 AM

Quote:

No it's like saying in a "True" quad core ALL four of the cores talk to each other inside the die and share resources. And with the C2Q they don't, Intel just put the two sockets usually on the mobo on the chip; BIG DIFFERENCE. It's like the differrence between PCI-E and NO PCI-E, hardly trivial. I'll try to make it even clearer: with Barcelona one core can use all 12MB of cache, two cores can use 6MB each, and four cores can use 3MB each; depending on workload.


What are you talking about.... of course they do (i.e. all cores in C2Q).... it is called cache coherency. All multicore systems must do this.... in a MCP they use the FSB backbone to snoop the caches....

AMD's monotlithic, discrete cache design is no different but uses the x-bar to cohere the cache.

You are speaking jibberish.

You sound like a two year old spurting clippets out of Computer Shopper.

"In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.", from http://en.wikipedia.org/wiki/Cache_coherency

This has nothing to do with whether there is a full sharing of cache resources in the first place. Since your probaby in complete denial i'll drop a spot from Intel that once again says what I said before about the C2Q. The two cores on each die share cache with each other; but not amongst the two dies.

"Intel® Advanced Smart Cache - Shared Level 2 cache across each pair of cores that can be dynamically allocated to each processor core, within the pair, based on workload. This efficient implementation increases the probability that each core within the pair can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.", from http://www.intel.com/products/processor/core2quad/prod_...

EXACT SAME AS A C2D
April 3, 2007 5:59:46 AM

Quote:
C'mon... it's almost six months after the intro of Business Vista and ATI still doesn't have a DX10 card out? That is completely unbelievable.


And people care? Vista blows, and there arent any DX10 games...AMD has time to spare. When Crysis is out and no R600..then you can complain.

And everyone seems to forget Intel has triple the amount of money and resources that AMD does..yet AMD still competes. AMD ripped apart Netburst..and now that intel has finally caught up you scream what has AMD been doing? If AMD had the resources Intel has..Intel would be out of business pretty fast.
April 3, 2007 6:35:51 AM

Quote:

You sound like a two year old spurting clippets out of Computer Shopper.

"In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.", from http://en.wikipedia.org/wiki/Cache_coherency

This has nothing to do with whether there is a full sharing of cache resources in the first place. Since your probaby in complete denial i'll drop a spot from Intel that once again says what I said before about the C2Q. The two cores on each die share cache with each other; but not amongst the two dies.

"Intel® Advanced Smart Cache - Shared Level 2 cache across each pair of cores that can be dynamically allocated to each processor core, within the pair, based on workload. This efficient implementation increases the probability that each core within the pair can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.", from http://www.intel.com/products/processor/core2quad/prod_...

EXACT SAME AS A C2D


Here, opterondo.. try to smarten yourself a little with people who know what the hell they're talking about:

http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2939

And here's an explaination of how the on die memory actually works:

Quote:
These days two Core 2 cores share up to 4MB of L2 cache, while the fastest offerings from AMD weigh in at half that. The gap will continue to widen with Barcelona, as each of its four cores will only have a 512KB L2 cache. While a quad-core Barcelona chip will have 2MB of total L2 cache for all four cores, a quad-core Kentsfield currently has 8MB of L2 cache for all four cores. By the end of this year, Intel's Penryn is expected to have 12MB of L2 cache for all of its cores.

In order to keep die sizes manageable, AMD constructed its quad-core Barcelona out of four cores each with a 128KB L1 and 512KB L2, much like most mainstream K8 based products today. However, the era of multithreaded applications demands that multi-core CPUs should have some common pool of high speed memory to keep them running at peak efficiency.

With four cores sharing a single die, AMD didn't want to complicate its design by introducing a large unified L2 cache. Instead, it took the K8 cache hierarchy and added a third level of cache to the mix - shared among all four cores. At 65nm, a quad-core Barcelona will have a 2MB L3 cache that is shared by all four cores.

The hierarchy in Barcelona works like this: the L2 caches are filled with victims from the L1 cache. When a cache gets full, data that was not recently used is evicted to make room for new data that the cache controller determines is good to keep in the cache. In a victim cache structure, the evicted data is placed in a storage area known as a victim cache instead of being removed from cache all together. If the data should become useful again, the cache controller simply has to fetch it from the victim cache rather than much slower main memory; victims from Barcelona's L1 are kicked out to the L2 cache.

The new L3 cache, acts as a victim for the L2 cache. So when the small L2 cache fills up, evicted data is sent to the larger L3 cache where it is kept until space is needed. The algorithms that govern the L3 cache's operation are designed to accommodate data that is likely to be needed by multiple cores. If the CPU fetches a bit of code, a copy is left in the L3 cache since the code is likely to be shared among the four cores. Pure data load requests however go through a separate process. The cache controller looks at history and if the data has been shared before, a copy will be left in the L3 cache; otherwise it will be invalidated.

Associativity hasn't been changed for the L1 and L2 caches; they are still 2-way and 16-way set associative, respectively. However, the new L3 cache is 32-way set associative. It has been designed to increase the hit rate of a relatively small cache compared to its competition.


To summarize: Barcelona basically cut all the individual core L2 cache (at 512KB each) and added an L3 cache (which is optional, 2MB max. for now) to handle the cross-swapping of data between cores. This adds another, 'outer' layer of memory for the cores to use ( L1>L2>L3). The cores do NOT completely (or even partially) share L2 caches. They share the L3. Intel uses the FSB to share between 2 L2 caches.

This seems to try counter Intel's deeper, larger caches (which can hold more data, and therefore, execute them more quickly) with smaller, recursive caches, which may work better with nested programs (small programs that perform the same small (2-3 ops)functions on large data lists).

Note that the Barcelona only has a total of 4.5 MB Cache on die, while a Kentsfield (Quad) has 8.5 MB and will soon have 12.5 MB.
April 3, 2007 6:36:31 AM

Its possible that your ability to properly implement Vista blows.... But Vista as we speak is a lot more stable than XP was at this stage of its implementation. I load XP once a month or so, just to keep it current.

As to the r600's... AMD IS grossly behind schedule, will not release anyone from NDA... So a paltry little is known about it. The same can be said of AMD's new cpu. In both cases, a lot of bragging, but no ES deliveries, no third-party benchmarks allowed.

Pardon me if I don't believe you when you say 'your cpu's better'n mine'. Show me the money, or leave the table.
April 3, 2007 7:14:53 AM

I hate these threads so much. If you have read this, forget everything you have read to this point. Buy a Mach3 razor. this is stupid.
April 3, 2007 7:32:32 AM

Quote:


Note that the Barcelona only has a total of 4.5 MB Cache on die, while a Kentsfield (Quad) has 8.5 MB and will soon have 12.5 MB.


I clipped the useless info you posted; I think we all can figure out L1 L2 L3. Barcelona will launch with 2MB L3 per CORE, thats 2MB x 4 CORES = 8MB L3 per DIE dynamically shared.
April 3, 2007 7:34:58 AM

Quote:
I hate these threads so much. If you have read this, forget everything you have read to this point. Buy a Mach3 razor. this is stupid.


I love these threads when they stay remotely on topic. I have used the Sensor Excel for 10 yrs but am thinking about trying the new Schick for a fling.
April 3, 2007 7:36:30 AM

Quote:


You sound like a two year old spurting clippets out of Computer Shopper.

"In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.", from http://en.wikipedia.org/wiki/Cache_coherency

This has nothing to do with whether there is a full sharing of cache resources in the first place. Since your probaby in complete denial i'll drop a spot from Intel that once again says what I said before about the C2Q. The two cores on each die share cache with each other; but not amongst the two dies.

"Intel® Advanced Smart Cache - Shared Level 2 cache across each pair of cores that can be dynamically allocated to each processor core, within the pair, based on workload. This efficient implementation increases the probability that each core within the pair can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.", from http://www.intel.com/products/processor/core2quad/prod_...

EXACT SAME AS A C2D


Wow.... you are quoting wikipedia to me.... :) 

You will need to do better than that. Intel's shared cache is not the same as cohering two (or more) discrete cache pools... they are two different things.
Intel C2Q shares L2 per die, AMD Barcelona will share L3 per die ..

Quote:
Barcelona, as you allude to above, cannot access all 12 megs, heck AMD is not even designing in 12 megs in the first iteration, they will have 512 KB discrete L2, 128 KB discrete L1, and 2 Meg L3 cache. The most 'dynamically' allocated cache Barcelona will do to start is 2 Meg, the L2 is still discrete and will need to cohere like any other discrete cache pool.

AMD Barcelona will share L3 per die .. four cores x 2MB L3 each core = 8MB L3 fully dynamic cache per die

Quote:
Cohrency of local (note Wiki's use of Local) cache across shared resources (meining main memory) --- you have selectively quoted wiki, misunderstood it, and did not read the entire description.... this is the first step to earning a title.

Once again coherence refers to the integrity of cache or memory of a shared resource. Not the actual sharing of said resource, yawn. Frankly your liberal use of unrelated terms shows that you think you are smarter than you really are.

Quote:
There is currently considerable interest in the computer architecture community on the subject of shared-memory multiprocessors. Proposed multiprocessor designs often include a private cache for each processor in the system, which gives rise to the cache coherence problem. If multiple caches are allowed to have copies simultaneously of a given memory location, a mechanism must exist to ensure that all copies remain consistent when the contents of that memory location are modified. In some systems, a software approach is taken to prevent the existence of multiple copies by marking shared blocks as not to be cached, and by restricting or prohibiting task migration.

http://www.cs.binghamton.edu/~shadi/cmp/papers/cache_co...

With this post you have now convinced me you do not understand the difference between shared cache and discrete cache.
You have convinced yourself .. once again liberal useless words; it's either shared or it's not.

Quote:
While I have not read this paper in detail in quite some time, it does show the difference between shared/tightly clustered cache systems and discrete, dedicated caches in SMT applications.

http://www-hydra.stanford.edu/publications/ISCA94.pdf

Go back to school, I reiterate --- you simply do not know what you are saying nor do you understand basics of multicore computing.

GBTS yourself, you sound like some 70YO military flunky that has to read 1500pg research papers to screw in a light bulb.

Quote:
BTW --- the base of my knowledge and the foundation of what I learn comes from more than 'clippets' from computer shopper, and a hell of a lot better than Wikipedia.


Yawn ..
April 3, 2007 7:54:17 AM

Quote:


You sound like a two year old spurting clippets out of Computer Shopper.

"In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.", from http://en.wikipedia.org/wiki/Cache_coherency

This has nothing to do with whether there is a full sharing of cache resources in the first place. Since your probaby in complete denial i'll drop a spot from Intel that once again says what I said before about the C2Q. The two cores on each die share cache with each other; but not amongst the two dies.

"Intel® Advanced Smart Cache - Shared Level 2 cache across each pair of cores that can be dynamically allocated to each processor core, within the pair, based on workload. This efficient implementation increases the probability that each core within the pair can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.", from http://www.intel.com/products/processor/core2quad/prod_...

EXACT SAME AS A C2D


Wow.... you are quoting wikipedia to me.... :) 

You will need to do better than that. Intel's shared cache is not the same as cohering two (or more) discrete cache pools... they are two different things.
Intel C2Q shares L2 per die, AMD Barcelona will share L3 per die ..

Quote:
Barcelona, as you allude to above, cannot access all 12 megs, heck AMD is not even designing in 12 megs in the first iteration, they will have 512 KB discrete L2, 128 KB discrete L1, and 2 Meg L3 cache. The most 'dynamically' allocated cache Barcelona will do to start is 2 Meg, the L2 is still discrete and will need to cohere like any other discrete cache pool.

AMD Barcelona will share L3 per die .. four cores x 2MB L3 each core = 8MB L3 fully dynamic cache per die

Quote:
Cohrency of local (note Wiki's use of Local) cache across shared resources (meining main memory) --- you have selectively quoted wiki, misunderstood it, and did not read the entire description.... this is the first step to earning a title.

Once again coherence refers to the integrity of cache or memory of a shared resource. Not the actual sharing of said resource, yawn. Frankly your liberal use of unrelated terms shows that you think you are smarter than you really are.

Quote:
There is currently considerable interest in the computer architecture community on the subject of shared-memory multiprocessors. Proposed multiprocessor designs often include a private cache for each processor in the system, which gives rise to the cache coherence problem. If multiple caches are allowed to have copies simultaneously of a given memory location, a mechanism must exist to ensure that all copies remain consistent when the contents of that memory location are modified. In some systems, a software approach is taken to prevent the existence of multiple copies by marking shared blocks as not to be cached, and by restricting or prohibiting task migration.

http://www.cs.binghamton.edu/~shadi/cmp/papers/cache_co...

With this post you have now convinced me you do not understand the difference between shared cache and discrete cache.
You have convinced yourself .. once again liberal useless words; it's either shared or it's not.

Quote:
While I have not read this paper in detail in quite some time, it does show the difference between shared/tightly clustered cache systems and discrete, dedicated caches in SMT applications.

http://www-hydra.stanford.edu/publications/ISCA94.pdf

Go back to school, I reiterate --- you simply do not know what you are saying nor do you understand basics of multicore computing.

GBTS yourself, you sound like some 70YO military flunky that has to read 1500pg research papers to screw in a light bulb.

Quote:
BTW --- the base of my knowledge and the foundation of what I learn comes from more than 'clippets' from computer shopper, and a hell of a lot better than Wikipedia.


Yawn ..

yeah...yawn..

get a sleep man. ur dreaming awake.

maybe ull be fine when ur wake up.

LOL!
April 3, 2007 8:00:57 AM

Quote:


You sound like a two year old spurting clippets out of Computer Shopper.

"In computing, cache coherence refers to the integrity of data stored in local caches of a shared resource. Cache coherence is a special case of memory coherence.", from http://en.wikipedia.org/wiki/Cache_coherency

This has nothing to do with whether there is a full sharing of cache resources in the first place. Since your probaby in complete denial i'll drop a spot from Intel that once again says what I said before about the C2Q. The two cores on each die share cache with each other; but not amongst the two dies.

"Intel® Advanced Smart Cache - Shared Level 2 cache across each pair of cores that can be dynamically allocated to each processor core, within the pair, based on workload. This efficient implementation increases the probability that each core within the pair can access data from fast L2 cache, significantly reducing latency to frequently used data and improving performance.", from http://www.intel.com/products/processor/core2quad/prod_...

EXACT SAME AS A C2D


Wow.... you are quoting wikipedia to me.... :) 

You will need to do better than that. Intel's shared cache is not the same as cohering two (or more) discrete cache pools... they are two different things.
Intel C2Q shares L2 per die, AMD Barcelona will share L3 per die ..

Quote:
Barcelona, as you allude to above, cannot access all 12 megs, heck AMD is not even designing in 12 megs in the first iteration, they will have 512 KB discrete L2, 128 KB discrete L1, and 2 Meg L3 cache. The most 'dynamically' allocated cache Barcelona will do to start is 2 Meg, the L2 is still discrete and will need to cohere like any other discrete cache pool.

AMD Barcelona will share L3 per die .. four cores x 2MB L3 each core = 8MB L3 fully dynamic cache per die

Quote:
Cohrency of local (note Wiki's use of Local) cache across shared resources (meining main memory) --- you have selectively quoted wiki, misunderstood it, and did not read the entire description.... this is the first step to earning a title.

Once again coherence refers to the integrity of cache or memory of a shared resource. Not the actual sharing of said resource, yawn. Frankly your liberal use of unrelated terms shows that you think you are smarter than you really are.

Quote:
There is currently considerable interest in the computer architecture community on the subject of shared-memory multiprocessors. Proposed multiprocessor designs often include a private cache for each processor in the system, which gives rise to the cache coherence problem. If multiple caches are allowed to have copies simultaneously of a given memory location, a mechanism must exist to ensure that all copies remain consistent when the contents of that memory location are modified. In some systems, a software approach is taken to prevent the existence of multiple copies by marking shared blocks as not to be cached, and by restricting or prohibiting task migration.

http://www.cs.binghamton.edu/~shadi/cmp/papers/cache_co...

With this post you have now convinced me you do not understand the difference between shared cache and discrete cache.
You have convinced yourself .. once again liberal useless words; it's either shared or it's not.

Quote:
While I have not read this paper in detail in quite some time, it does show the difference between shared/tightly clustered cache systems and discrete, dedicated caches in SMT applications.

http://www-hydra.stanford.edu/publications/ISCA94.pdf

Go back to school, I reiterate --- you simply do not know what you are saying nor do you understand basics of multicore computing.

GBTS yourself, you sound like some 70YO military flunky that has to read 1500pg research papers to screw in a light bulb.

Quote:
BTW --- the base of my knowledge and the foundation of what I learn comes from more than 'clippets' from computer shopper, and a hell of a lot better than Wikipedia.


Yawn ..

yeah...yawn..

get a sleep man. ur dreaming awake.

maybe ull be fine when ur wake up.

LOL!
April 3, 2007 8:13:52 AM

Quote:
Except your off a generation P4 vs. K8; P4D vs. K8L; C2D vs. K8L -- see the problem with your logic.


Umm...what the hell are you smoking?

K8L has been cancelled and was never even released! So saying that P4D was designed to compete with the K8L is just retarded.

K8L was the name that was associated with AMD's new technology product, now named K10, so.... K8L was not canceled, it is the Barcelona core.
April 3, 2007 8:34:03 AM

'Mythical' Barcelona core..... 'Mythical' r600 GPU.... Hypothetical also comes to mind. Speculative, etc.

Until we see third party benchmarks on these 'mythical' products, until we can go to a store and buy them, then they are just rumour and propaganda.

Please don't respond to this without facts in hand.
April 3, 2007 8:41:32 AM



9nm? 8O
April 3, 2007 8:55:07 AM

Quote:
9nm? 8O


Stop boasting about the size of your kurac.

:twisted:

Just kiddin' dude. Don't kill me! :lol: 
April 3, 2007 8:59:56 AM

Quote:
'Mythical' Barcelona core..... 'Mythical' r600 GPU....


So do you think that there is truth behind the rumour that Hector is about to replace Henri Richard with J.K. Rowlings? At least J.K. is more experienced in concocting fantasy scenarios! :lol: 
April 3, 2007 9:13:17 AM

hay I m going to make you look like a fool Opterondo and it will be wikipedia that make you so. Teachers are Finding there Children useing info Wikipedia and there school work and due to this Teachers warn students that the info is not %100.

Put it this way. You can log onto Wikipedia and edit it. Look at the top Article Discussion Edit this page History. Let read this part.

Because Wikipedia is an ongoing work to which in principle anybody can contribute, it differs from a paper-based reference source in some very important ways. In particular, older articles tend to be more comprehensive and balanced, while newer articles may still contain significant misinformation, unencyclopedic content, or vandalism. Users need to be aware of this in order to obtain valid information and avoid misinformation which has been recently added and not yet removed.
April 3, 2007 9:30:55 AM

Honestly I don't care who runs the corp.... I just wish someone would run the corp, do what they are supposed to do, instead of running only their PR based mouth.

I've heard PR 'til its coming out of my ears. 'Where's the beef???'

Buyers cannot deal on speculation. Even we low end buyers. I'll upgrade later this year, to whatever is AVAILABLE AND HAS THE BEST BOTTOM LINE at the time that I need to upgrade. I am only buying one unit, for me.... But my decision is no different to a corp. buying thousands. If I can't get it, if I can't even get reliable benchmarks, ...

'Pig in a poke' comes to mind.
April 3, 2007 9:46:09 AM

Quote:
'Mythical' Barcelona core..... 'Mythical' r600 GPU....


So do you think that there is truth behind the rumour that Hector is about to replace Henri Richard with J.K. Rowlings? At least J.K. is more experienced in concocting fantasy scenarios! :lol: It would be good. :D  :D  :D 

April 3, 2007 9:48:53 AM

No doubt that Intel is the current performance king.

AMD's upcoming chip looks like it will level the playing field a lot (stronger FP and better caching). Some of the benchmarks on Barcelona make it look like it'll perform simiarly to Core (better in some areas, worse in others).

Still their new chip just an evolution of their current core, not a completly new one. A lot has changed in CPUs in the last 5 years, AMD will be needing a new core in the next year or two to continue to compete.
April 3, 2007 10:13:55 AM

Quote:
AMD will be needing a new core in the next year or two to continue to compete.
Not a new core, but a core upgrade and higher frequencies.
April 3, 2007 11:16:56 AM

Quote:
Honestly I don't care who runs the corp.... I just wish someone would run the corp, do what they are supposed to do, instead of running only their PR based mouth.

I've heard PR 'til its coming out of my ears. 'Where's the beef???'

Buyers cannot deal on speculation. Even we low end buyers. I'll upgrade later this year, to whatever is AVAILABLE AND HAS THE BEST BOTTOM LINE at the time that I need to upgrade. I am only buying one unit, for me.... But my decision is no different to a corp. buying thousands. If I can't get it, if I can't even get reliable benchmarks, ...

'Pig in a poke' comes to mind.


When Swatch presented their Swatch Talk watch-phone at Cebit in 1998 at least they had one physical item to demonstrate. Yes, 9 years have elapsed and the product hasn't found its way to market yet, but at least you can give Swatch credit for cobbling together one working prototype. AMD hasn't even gone that far with R600 and Barcy/Agena/Whatchamacallit. There is zero credibility, zero product, zero benchmarks and absolutely zero beef! There's no beef. There's lots of air, but no beef.

Quote:
It would be good. :D  :D  :D 


Very nice work, Tanker. I'm proud of ya.

Quote:
Some of the benchmarks on Barcelona make it look like it'll perform simiarly to Core.


Benchmarks? Benchmarks? Where are the Barcy benchmarks? Did I miss them? Was I sleeping? :lol: 
April 3, 2007 2:27:30 PM

Quote:

AMD Barcelona will share L3 per die .. four cores x 2MB L3 each core = 8MB L3 fully dynamic cache per die.


NO, idiot, there is a TOTAL of 2 ( TWO ) MegaBytes L3 cache shared by all 4 ( FOUR ) cores. NOT 2MB per core.
RTFM!

Quote:
GBTS yourself, you sound like some 70YO military flunky that has to read 1500pg research papers to screw in a light bulb.

And you "sound" like some stupid 13 year old punk that doesn't know how to read. If you can't be bothered to read the article, and I even quoted the most relevant part of it in whole, then you qualify as a MORON, and need to STFU. Either back it up, or shut up.
April 3, 2007 2:48:26 PM

Quote:
Benchmarks? Benchmarks? Where are the Barcy benchmarks? Did I miss them? Was I sleeping? :lol: 


Oops hadn't realised they still wern't published. Sorry can't give any more specfics but they are good.
April 3, 2007 4:38:27 PM

Quote:
Benchmarks? Benchmarks? Where are the Barcy benchmarks? Did I miss them? Was I sleeping? :lol: 


Oops hadn't realised they still wern't published. Sorry can't give any more specfics but they are good.

Given their new editorial focus, I've been sent by the THG editors to Bavaria to roadtest the new BMW 950i. It's due out sometime in 08 or maybe 09. It has a 538 hp V10 engine that uses water as fuel, a computer that does all the driving for you, and telescoping wings so you can fly to your destination. Sorry can't give any more specfics but they are good.

:lol: 
April 3, 2007 5:27:05 PM

Quote:
IMHO this is exactly Intel's strategy. To kick AMD while it's down and unable to get up. It's more of a mugging than competition. But all's fair in war and business!


"All" isn't fair in war and business... but in this instance, yeah... Intel is doing what any smart business would do. Would you rather fight Mike Tyson when he's 21 or when he's 80 and in a nursing home? There are rare exceptions to this idea of kicking your opponent while they're down... look at Toyota... they're being ultra-cautious when dealing with GM/Ford... the last thing they want to do is destroy those American manufacturers and risk a huge PR backlash. If AMD folded (I said IF) as a result of Intel's price/performance war, a vocal minority would be pissed but most wouldn't really care. We just want faster computers and low prices.
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