I don't post often, but I lurk a lot. There's one thing I've been wondering which hasn't been talked about (as far as I can tell). Intel's C2D Conroe contains 4MB of shared L2 cache, shared between 2 cores. But from what information I've been able to find, AMD's Barcelona will have a 2MB shared L3 cache, shared between 4 cores. This sounds rather small. Has anyone done any kind of comparative analysis of the effect of such a small cache, and it being L3 instead of L2? The closer to the CPU you can put fast memory, the better, so sharing at L3 instead of L2 is also bad, right?