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I stumbled on this article while doing some reading, funny thing is it was linked by The Inq , but the article itself is really interesting.
It explore transistor performance versus interconnect performance. As the process shrink, the interconnect delays get bigger and bigger. A 3D design is proposed to alleviate the problem.
Altough the subject is rather advanced, I find it's nicely explained and easy to follow. There is some very intersting data on a "3D P4" that intel developped.
http://realworldtech.com/page.cfm?ArticleID=RWT050207213241
It explore transistor performance versus interconnect performance. As the process shrink, the interconnect delays get bigger and bigger. A 3D design is proposed to alleviate the problem.
Altough the subject is rather advanced, I find it's nicely explained and easy to follow. There is some very intersting data on a "3D P4" that intel developped.
http://realworldtech.com/page.cfm?ArticleID=RWT050207213241