turpit :
There are some big advantages with MCM, that would have benefited AMD greatly had they been able to implement it. As far as the disadvantages, bus saturation and 'cache thrashing' so loudly 'hyped' by AMD and the fanboys; cache thrasing turned out to be nothing but BS hype, and bus stauration hasnt proven to be a problem.
There have been many threads about why AMD can't do an MCM (that would work well), so no point in rehashing that. But AMD *did* make two independent memory controllers in the 10h chips and that does allow for MCMs to be made while keeping the same sockets. (Each die would have one IMC active and one deactivated and communicate over an in-package HT link.) In fact, AMD has an eight-core MCM in their roadmap. I believe it is called "Montreal."
The cache thrashing did turn out to be a non-issue, but IIRC a shared L2 had never been done before and it didn't sound unreasonable. Bus saturation isn't much of an issue with the UP chips, but move to more sockets and cores and that becomes less and less true. By the time there are four dies on two FSBs in an Intel Clovertown dual-quad-core or Paxville MP quad-dual-core setup, bus saturation is certainly rearing its head versus a quad dual-core Opteron setup.
@Conroe: x86 probably isn't the world's greatest ISA and certainly wasn't when it debuted, but it has been modified enough to do the jobs we ask of it pretty decently. An all-new rewrite isn't necessarily better- the Itanium was and it is a pretty poor general-purpose CPU. There have been some instructions added, mostly in the form of SIMD ops, but I'd much rather have additional packed instructions like SSE rather than a one-operation-per-issue-per-clock-cycle pure RISC chip. And x86_64 cleaned up the old x86 ISA quite a bit as well. It's still not very nice to do assembly on, but assembly is generally only used for embeddable stuff today anyway.