Really need some help on temps, E6850

Core temps.

If you've read the Core 2 Duo Temperature Guide http://www.tomshardware.com/forum/221745-29-core-temperature-guide then you know that Offsets can be adjusted from within SpeedFan. The CPU and Core temps can be greatly affected by whether or not PECI (Platform Environmental Control Interface) is enabled. Afterword, your CPU temp should Idle just a degree above Ambient, and the Cores should run ~ 15C above the CPU at 100% TAT Load.

Hope this helps,

Comp  

Thanks - I will just go with the core temp values.

I did read the guide, which is why I was concerned. The cpu readings do not come close to 15C below cores and in fact is 20C higher than the core temps at load. I could not find any settings for PECI in the bios.

Tried re-installing the heatsink for the fourth time and what a difference. CPU now idling at 33 with cores running 21-24c. At 100% load, cpu at 51c and cores 41-43c.

I had sent Intel tech. support a messge when cpu temps were up at 70c and asked for their input. Below is their reply;

----------------------------------------------------
Thank you for contacting Intel(R) Technical Support.

It is completely normal to see variations on the core temperature and the CPU temperature.

You mention that the (CPU temp jumps to 70C while the core temps are at 50C), this behavior is completely normal since the processor is still running under the processor specifications, please remember that the maximum recommended temperature of your Intel(R) Core(TM) 2 Duo processor E6850 is 72 Degrees Celsius. At this point your processor is not even having overheating issues.

The fact that the CPU temperature is above the core temperature is not an issue, since as mention above this is a normal behavior.

For more thermal information regarding Intel(R) Core(TM) 2 Duo processors please check the Thermal design guidelines located at the following document:
http://download.intel.com/design/processor/designex/317...

S incerely,

Adolfo S.
Intel(R) Technical Support

Intel(R) Processor Support Web Site:
http://support.intel.com/support/processors/index.htm

Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.
-----------------------------------------------------

I can't seem to reconcile this with the temperature guide which indicates cpu temps should always be lower than core temps. I am relatively new at this and would like to understand - all guidance is appreciated!

Cooperstown39, sorry it's taken so long to get back to you. Tcase (CPU) temps are important because there is a defned relationship between Tcase and Tjunction (Core) temps, since the accuracy of one verifies the accuracy of the other.

Intel's response, while lame and very dissapointing in this instance, (since your Tcase and Tjunction temps are both wrong, and most certainly are NOT normal), is also not surprising. I am aware of countless such responses which are evasive, incomplete, uninformative, vague, inaccurate, and / or misleading, and all too often disagree, or are inconsistent with other emails concerning like or identical topics answered by different Intel Reps.

Further, Intel's Specifications sometimes have discrepancies which don't make any sense, (E6400 L2 Stepping), and the information contained in the thousands of pages of documentation I've read, often contains text which conflicts with other Intel papers. Attempting to obtain answers which are accurate, unconflicted, and uniform from Intel is often more diffucult than obtaining the recipe for the First Lady's chocolate chip cookies from the CIA. So let's move on, use our heads, apply some common sense, and review Thermal Flow.

As I've outlined in the Guide, NO temps can be less than Ambient. Heat originates (and is measured by the DTS sensors as Tjunction) within the hot spot of each Core, and is dissipated throughout the CPU Die, Heat Sinc, Socket and Motherboard, hence, a thermal gradient exists between the Cores and the on-die Tcase thermal diode, (located between the Cores), where the temperature is ~ 15c cooler, + / - 3c.

If your Ambient is at the desired PC operating environment of 22c, and set at low Vcore and clock, then with mid-range to high-end cooling, Tcase MUST Idle just very slightly above Ambient, and Tjuction MUST Idle ~ 12c to 15c higher than Ambient. Since Tcase to Tjunction Delta is typically ~ 20c, depending upon Vcore, clock, cooling and Load, then your temps should resemble the following:

Ambient = 22c
Tcase (CPU) Idle = 23c
Tjunction (Core) Idle = 38c (Hottest Core)

Tcase (CPU) Load = 43c
Tjunction (Core) Load = 58c (Hottest Core)

Tcase to Tjunction Delta = 20c

As you can see, these temps make sense, and I assure you, are typical on systems free of manufacturer's hardware / firmware / software dicrepancies. Systems which fail to show these results obviously have discrepancies, which are known as "Offsets". Fortunately, since the release of SpeedFan 4.32, both Tcase and Tjunction values can be corrected.

I recommend that you calibrate your temps using the "Offsets" section of the Guide, and by using the following steps:

(1) Set BIOS for 1.8 Ghz, 1.25 Vcore, all fans 100%.

(2) Note CPU temp in BIOS, start Windows, Idle 10 minutes.

(3) Measure Ambient temp, preferably near computer air intake.

(4) Remove computer case covers, note Tcase (CPU) temp, should still agree with BIOS + 0c to 2c.

(5) Configure SpeedFan Offset for Tcase (CPU) = Ambient + 1c.

(6) Configure SpeedFan Offsets for Tjunction (Cores) = Ambient + 15c (Hottest Core).

(7) Restore BIOS to Test settings shown in Guide, run TAT or Orthos. Temps should not exceed Tcase (CPU) 50c, Tjunction (Cores) 65c unless abnormally high Ambient and / or Vcore.

Due to differences in Tjunction Max 85c or 100c Specifications relative to various Steppings, Tjunction inaccuracies tend to be off by either 15c or 30c, but are also known to typically be erroneous in 5c increments. Since your Tjunction Idle temps are in the low 20's, this would seem to indicate a +15c Offset is required.

Hope this helps,

Comp  

Comp, thank you for the reply and detailed explanation. It makes sense and certainly more helpful than anything I have gotten from Intel. I will spend some time next weekend to configure the Offsets, as per your instructions. This is now the second time you have helped me with temperature questions and it is greatly appreciated.

At the risk of "overextending my welcome", can you explain the location and difference between the temp. diode (Tcase) and dts (Tj) sensors? Just curious if these are small sensors built in to the package or if they are actually part of the chip design??

Again, thanks for the help!!

Coop

Boy CompuTronix nailed it! Its sad to see the response from Intel.

Cooperstown39, to put things into perspective, C2D's have nearly 292,000,000 transistors. Each Core is a fraction of the size of the hologram on a credit card. In the world of 65 nanometer architecture, 10's of thousands of the basic components of electronics are etched within progressive layers. Capacitors, inductors, resistors, diodes, transistors, and their PN (Positive / Negative) junctions, which comprise more complex devices such as processor registers and cache memory, can only be observed through a powerful microscope. As an engineer, I can tell you that the vast majority of people fail to grasp the overwhelming complexity involved in electronics.

Now that you can begin to visualize nano scale, the Digital Thermal Sensors (DTS) are thermal diodes, which are integral components of the Core 2 design, located within the "hot spot" of each Core. These hot spots actually change locations, depending upon processor tasking and load, so the DTS's are more acurately described as being located where the "average hot spot" is usually located. This implies that under certain tasking conditions, Core temp (Tjunction) may not indicate the highest actual Core temperature at certain moments, and that elsewhere within the Core, the temp is somewhat higher. This is why specifications are written to include very precise tolerance considerations. Since both Cores are fabricated to be an integral part of the larger CPU "Die", the Die itself behaves as a heat sinc for the Cores, due to it's greater mass and thermal conductivity, thus the "thermal gradient" between Tjunction and Tcase.

With respect to CPU Case Temperature (Tcase), Intel's papers show detailed images and descriptions of how the (Integrated Heat Spreader) IHS, (the processor's top cover), is cut and "grooved" to accomodate wires and a "thermocouple" in the top center, which is then sealed and "lapped" into a flush condition, in order to conduct controlled laboratory thermal performance tests with Intel's boxed CPU cooler. Since this test setup is unavailable to those of us outside the laboratory, the Case Thermal Diode is used to measure Tcase.

It is noteworthy to add that both the DTS (Digital Thermal Sensor) circuitry and the CTD (Case Thermal Diode) use an analog thermal diode with a + / - 1c accuracy; the difference being that the DTS Analog to Digital conversion (A to D) is performed on-chip, and the CTD conversion is performed off-chip by the Motherboard's Super I/O chip. The CPU Case Thermal Diode is located under the bottom center of the IHS, imbedded in a layer at the top of the CPU Die, between the Cores. Since this is the next best position compared to the laboratory test setup, there is a slight difference in temperature between IHS top center, and Die top center, so the need for acurate BIOS thermal tables becomes obvious.

When Tcase and Tjunction temperatures are inverted, or below Ambient, or don't comply with norms or parameters, it's also obvious that inaccuracies exist, so calibration procedures and offset corrections become necessary. In the Guide, I recommend SpeedFan because it's one of the few utilities which allow offset corrections, and which also provides excellent configuration flexibility. Even Motherboards with the most severe temperature discrepancies can be calibrated to display accurate temperatures. I will be adding a new "Calibration" section to the Guide in the not-too-distant future, so please watch for updates.

Hope this answers your questions,

Comp  

Great explanation and THANKS!! You are correct that the scale of the chip is hard to grasp. Wait till you see the 32nm processes with the low-k (possibly porous) dielectric and high-k replacement for the gate ox.