Computronix M0 steppings are not Tj max 85c

[gigabyte128]

Hi, I have seen your updated guide posted on Overclock.net by another member there and I see your guide suddenly changed Tj max for M0 steppings to 85c Tj max and delta to 5c. I have the E4500 which is M0 and only M0, Tcase is already correct by doing the underclock and undervolt testing. There is several problems..

1. Why would the L2 stepping of E2xxx/E4xxx have a Tj max of 100c when their Tcase max is only 61c. While the M0 stepping of E2xxx/E4xxx have a Tj max of 85c when their Tcase max is 73c? The M0s steppings have better thermal tolerances somthings not right there..

2. When on load reguardless of overclocked, stock or underclocked, Tcase is always higher than cores, this is going by the proposed 85c Tj max. We all know cores are always higher than Tcase as they are the heat source. Its like saying the air just above a fire is hotter than the fire itself.. not. 85c Tj max for M0 just does not compute at all.

3. Now that you changed the delta, 100c Tj max isn't fitting anymore (I still believe its 100c with a 10c delta untill I see some proof of a different Tj max that fits "properly"), but a 95c Tj max fits exactly perfect with the 5c delta and with the temp scales on your guide. Consider looking into this?

I would also like to know how do you generate your list of Tj max? Intel hasn't released any info for desktop processors yet about this, and as we can all see theres a war already about what Tj max is what on what processor.

RealTemp can be found here: http://www.xtremesystems.org/forums/showthread.php?t=179044 They seem to be bashing CoreTemp pretty hard, while they got no proof that CoreTemp is wrong and theirs is right

 

[crrust]

I am the one reposting your temp guide on OCN, with full credit to you and Tom's Hardware forums of course. I would also like to know where you come in on the TjMax argument. I just had a 2 day battle over this issue with a member from ExtremeSystems. Based on documentation from Intel and testing by him and others he is arguing firstly that the delta between Tcase and Tjunction is more on the line of 1°C as opposed to 5/10/15°C. His own testing has shown that the TjunctionMax for his E8400 is roughly 95°C and not the 105°C that we believe it to be. Anyway, any insight you have on this would be appreciated.

 

[CompuTronix]

gigabyte128 and crrust, thank you for your questions. Unfortunately, I've had no time during the past 2+ weeks to devote to the Forums, nor do I have time presently, however, please be patient, as I expect to be in a position to respond in detail later this week.

crrust, although I appreciate your interest in my Temp Guide, and I'm aware of the efforts you've already put forth at OCN, I do not wish for the Guide to be deployed or otherwise "reposted" for a very simple reason; since I frequently update the Guide, and am planning on once again doing so very soon, it will shortly be outdated. Therefore, in order to uniformly provide updated information, please remove my "reposted" Guide from OCN, and instead replace it with a link to my Guide here at Tom's.

Thank you in advance for your cooperation,

Comp

 

[crrust]

I understand and will remove it if you wish, but I wonder if we might not reach a small compromise =) I am fairly vigilant in updating the reposted version as you update the original, but in the event of an update by you that I miss would it be acceptable for me to preface the reposted version with a direct link and note that the link is to the most current version?

My hesitation in removing it completely is my belief in its value. Your guide is a great resource for temperature information and I really hate to remove it completely from OCN. If this is still not acceptable to you then I will remove it of course. Thanks for your consideration.

 

[gigabyte128]

I also forgot to mention the stock voltage on M0 stepping E4xxx processors is 1.2000v, at least mine is. Bios and CoreTemp says stock volts is 1.2000v and they get that info right out of the CPU itself.

 

[gigabyte128]

Ok I got a thread from Overclock.net with a member using an E6600. His Tcase is higher than the cores by about 15c, Tcase for his CPU is supposed to be about 15c below the cores, this is very abnormal. He has tried enabling/disabling PECI in bios and it has had no effect, the only thing I can think of is B2 stepping E6600 do not have a 85c Tj max, but I strongly believe they do.

The thread can be found here: http://www.overclock.net/intel-cpus/305773-e6600-temps-2.html

 

[CompuTronix]

gigabyte128, please ask the user to calibrate his rig according to my Guide here at Tom's. I have simplified the calibration procedure, so users will find it easier to follow. Also, I have just completed an extensive update to the Guide, so I was just about to ask you and crrust to review it and give me your opinions.

Comp

 

[crrust]

Printing it now =) I will update the OCN post and read the new version tonight. I gave it a quick scan and it looks like you put a lot of changes in!

 

[CompuTronix]

crrust, please proceed with your proposed compromise by including the link and note at OCN. The primary objective is always to help as many users as possible to understand how temperatures work, and to get as many rigs calibrated as possible.

Again, thanks for your interest. I appreciate all the help I can get. Let me know what you think of the update.

Comp

 

[gigabyte128]

I do not see anything changed in your guide, it still says last updated in Feb.

EDIT: I refreshed the page and it magicly updated! Ignore what I said above

 

[gigabyte128]

I have just reread several parts of the guide, I notice you say Tj max is 85c - 95c, but you have not specified which Tj max is on what series. I know M0 stepping E4xxx/E2xxx have to be Tj max 95c as that is the only Tj max that correctly fits in going by your guide and common sense.

Another question, you said Intel has validated that Tj max are 85c - 95c on current Core 2's. Has Intel finally released some info reguarding the large confusion about Tj max? As I still can't find any info on this by Intel.

Thanks, and I love the update you have done on your guide, many temps make more sence now.

EDIT: So because Tj max of 95c is the only one that correctly works with M0 steppings a Speedfan Tjunction offset of 10c will be needed instead of 15c correct?

 

[rge]

I just had a 2 day battle over this issue with a member from ExtremeSystems. Based on documentation from Intel and testing by him and others he is arguing firstly that the delta between Tcase and Tjunction is more on the line of 1°C as opposed to 5/10/15°C. His own testing has shown that the TjunctionMax for his E8400 is roughly 95°C and not the 105°C that we believe it to be. Anyway, any insight you have on this would be appreciated.

That would probably be me, and let me clarify.

The delta from tcase to tjunction depends on whether a heatsink is in place or not. If you place a hot probe on one side of a thin copper block, and measure the temp on the other, only a small gradient will be measured. If you place a hot probe on one side and actively cool the other, a larger gradient will be measured. A heatsink actively cools tcase, and therfore to approximate core temp, we measure Tcase...
1) with heatsink off, otherwise you are cooling tcase and creating gradient.
2) at idle steady state to minimize any gradient (slowly bring to idle and allow steady state..with E8400, .9v and 6x200 works well)

From intel papers...The gradient from core sensor to between the cores (across die)...is less than 0.1C at idle steady state, and in fact, ~15% of tested programs at load steady state, and nearly 1/3 tested "popular programs" by intel at load steady state had less than 1C gradient...figure 5 in below link...but read whole paper from intel
http://arxiv.org/ftp/arxiv/papers/0709/0709.1861.pdf
Intel felt this 5c max gradient requiring a constant offset if temp measured via diode, was worth moving to DTS to recoup this "4 to 7%" loss in efficiency.

The gradient from thermocouple on die (via hole drilled to it) to casing temp was measured in one experiment...and found to be 0.4C, again steady state idle, no cooling.
http://www.overclockers.com/tips443/

Or you can approximate the gradient at steady state idle from die to tcase from reading several intel papers (and knowing the intel paper above shows gradient across die is <0.1C at steady idle), One paper...
http://www.flomerics.com/flotherm/te...apers/t324.pdf
Thermal conductivity [W/m-°K] of die is 120.4, die attach adhesive is 0.9, mold compound is 0.63, air is 0.0261. Gradient measured from tj4 (68C) to tc (67.9C) was 0.1C across ~130um of mold cap. Temp gradient should also be nearly 0.1C across 75 microns of die attach adhesive (higher conductivity and thinner).

It would be hard to believe a gradient higher than 1C then by just increasing the thickness of the IHS, especially given intel has been researching for years/making improvements to minimize this gradient on load. Though Intel in various papers test and list thermal conductivity for silicon die, ceramic die, die attach adhesive, IHS compound, etc, no proof exists they are using these exact ones, but I doubt they are using ones less effective than ones they have published/successfully tested.

This shows that a gradient likely less than 1C exists from core to tcase WHEN TCASE IS NOT COOLED BY A HEATSINK AND AT STEADY STATE IDLE UNDERVOLTED AND UNDERCLOCKED, which is how we are doing our measurements. When you apply a heatsink, and actively cool tcase, a higher gradient exists than 1C.

As an aside, cpu temp is an attempt to approximate Tcase, but may not completely. True Tcase position is actively cooled by heatsink/waterblock. CPU temp for E8400 (no diode) is approximated usually from a mobo sensor under and abutting the cpu socket, thus that temp position is not directly cooled by the heatsink as tcase, but is instead calibrated to approximate such.

 

[CompuTronix]

CPU temp for E8400 (no diode) is approximated usually from a mobo sensor under and abutting the cpu socket,

rge, from Intel's Processor Spec Finder for the E8400: http://processorfinder.intel.com/details.aspx?sSpec=SLAPL

These parts have PROCHOT enabled.
These parts have THERMTRIP enabled.
These parts have PECI enabled.
These parts have Tdiode enabled
These parts have Intel® Trusted Execution Technology (Intel® TXT) enabled
These parts have Extended Stop Grant State (C2E) enabled
These parts have Extended (C4) enabled

Intel specifies that Tdiode is present on the E8400, just as it is on previous Core 2 processors.

Comp

 

[rge]

Thermal specs of E8400 per white sheet from intel, a direct quote
"Note: The processor has only DTS and no thermal diode. The TCONTROL in the MSR is relevant
only to the DTS."

http://download.intel.com/design/processor/designex/31873401.pdf
page 39, see under graph

 

[CompuTronix]

Yes rge, Iv'e read that some time ago, however, it seems that Intel is providing conflicting information, as the Thermal Specification remains the same as it is for previous Core 2 processors.

 

[gigabyte128]

Tdiode is for sure enabled on all Core 2's if it wasn't we woulden't have our Tcase reading. It is not related to the Tjunction reading from thr DTS in such the way you said.

 

[CompuTronix]

gigabyte128, are you responding to rge?

 

[gigabyte128]

Yes, sorry I wasn't more clear.

 

[CompuTronix]

Thanks. I've just completed another update to the Guide which involves a change to the methodology by which calibrations are performed. The Guide calibrates SpeedFan between Core Temp and Real Temp, so unclewebb might find it interesting. I'd like to know what you think. Care to give it another read?

 

[rge]

http://www.xtremesystems.org/forums/showthread.php?t=179044&page=23
here at post 562 I quoted my references. But I think I know why Gigabyte and others are feuding over tjmax, they have different tjmaxes based on different cpuids.

Tjmax C = Tcasemax C + (thermal resistance from tj to tcase C/W x TDP max W)
pic, etc in link at xtreme.

Interestingly if take my E6850 and fill in numbers, you get
tjmax = 72C + (.38c/w*65W) = 96.7C, c/w figure based on intel specs for each, though using c-a instead of j-t, I believe since cooling solution is what drives the tcase figure, it may be relevant to use such, also adding up other quoted resistances gets you close to this figure...though it will vary from part to part, dont believe it is huge variance.
but add in the testing that is done with ? individual/batch corrections such as here http://www.yeongyang.com/report/RPG-...516-05)RPG.pdf ...and could be either still.

E6x50 and E6540 with 4mb L2 and CPUID ending in 6FB
tjmax = 72C + (.38c/w*65W = 96.7C

And For E4000 series with CPUID ending in 6FD or 6FB (CPUID read by coretemp)
tjmax = 73.3 + (.38x65) = 98C

For E4000, E6000 series with CPUID ending in 6F2 or 6F6
tjmax = 61.4 + (.38x65) = 86.1C

E6000 CPUID 6f6 and 4mb L2
tjmax = 60.1 + (.38x65) = 84.8C

E8400
tjmax = 72 + (.38x65) = 96.7C

Unclewebb can you confirm your CPUID, I am betting you tested a 6F2 or 6F6 (if E4000 or E6000), and Gigabyte has 6FD or 6FB for his E4000. I can not be 100% sure of c/w, but I am pretty sure there is at least a ~12C difference in tjmax between those two cpuid, because the formula is correct, even though both e4000 series.