VHDL component help

I am trying to create an 8 bit alu for my first ever vhdl assignment, and I'm having trouble implementing a structural adder inside my alu. I have the 8 bit adder working fine but I don't know how to make the 2 inputs of the adder use the 8 bit adder when the opcode is "0000". I have a case statement to implement the opcode. Any help or suggestions would be great.

ALU code so far:




--ARITHMETIC LOGIC UNIT


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity eightbitalu is
port (aluin_a, aluin_b: in std_logic_vector(7 downto 0);
C: in std_logic_vector(3 downto 0);
C_in: in std_logic;
alu_out: out std_logic_vector(7 downto 0);
zero: out std_logic;
C_out: out std_logic
);
end eightbitalu;

architecture my_eightbitalu of eightbitalu is

component Adder8
port (A, B: in std_logic_vector(7 downto 0); Ci: in std_logic;
S: out std_logic_vector(7 downto 0); Co: out std_logic);
end component;

signal temp_out: std_logic_vector(7 downto 0);


begin
alu_out <= temp_out;

ADD: Adder8 port map(A=>aluin_a, B=>aluin_b, Ci=>C_in, S=>temp_out, Co=>C_out);

process(C,aluin_a,aluin_b)

begin

case C is

when "0000" => I NEED TO ADD ALUIN_B+ALUIN_A USING THE 8BIT ADDER
when "0001" => temp_out <= aluin_a + aluin_b + C_in;
when "0010" => temp_out <= aluin_a - aluin_b;
when "0011" => temp_out <= aluin_a - aluin_b - C_in;

when "0111" => temp_out <= "00000000";
when "1000" => temp_out <= aluin_a or aluin_b;
when "1001" => temp_out <= aluin_a and aluin_b;
when "1010" => temp_out <= aluin_a xor aluin_b;
when "1011" => temp_out <= not aluin_a;
when others => NULL;


end case;

end process;

end my_eightbitalu;