Wouldn't a smaller cache size work much more efficiently than a large cache when doing a LOT of multi-tasking?

Bigger cache sizes will give better results in the currently available benchmarks. But is this at the detriment of "smoothness" while task switching? (Call it Cache Thrash?)

With 4 cores... this inefficiency is probably hidden because there is enough horsepower sitting around that this won't show up. At least not until a benchmark is created to actually test for multi-tasking efficiency.

Currently it appears most benchmarks that actually have multi-tasking tests are really just testing how several tasks can work on several processors. They don't appear to add enough tasks to require a lot of TASK-SWITCHING. But then this issue might start showing up when doing hardware virtualization... the smaller cache sizes might be better when doing a lot that.)

Actually I don't know about the hardware virtualization stuff currently... I'm not up to speed on that. (Although it would be VERY COOL to boot Windows and Linux on the same machine. If I could work in Windows to use the Business Objects Data Integrator while running a database in Linux... I would be loving that.)

ANYWAY ANOTHER QUESTION: If the smaller cache is better for actual multi-tasking... why are the cache sizes getting LARGER in the newer Quad chips?

no
from what i have seen sometimes bigger does not add any improvement or very little. i never seen bigger is lower performance

now therertically - i suppose yes

Where are you pulling this backwards logic that smaller cache is better for "task switching"? And FYI, there's no such thing as "cache thrashing", it was a term made up by shakiraboob during a drug fueled rant against the blue team.

Where? From the fact that it is true.

If the cache has the task of keeping memory for a job... and that job instantly changes... then everything in the cache is no longer relevant and must now be flushed and now we have to keep track of the NEW job.

If the cache has a lookahead buffer... then the situation is exacerbated. With a LOT of switching tasks back and forth the cache could indeed thrash.

FYI: The term "cache thrashing" is a valid term and was not made up by somebody in this forum. (I was just throwing the term in because it rhymed and I was being a smart aleck... but it does actually describe a situation that arises in low associativity caches.)

well i really dont know about how intel or amd dual quad cores work, but until now i assumed that each core has a L1 internal cache for itself, for these small self trheads/virtualizations etc, and they also share a big cache of l2 and or l3, or any combination of it, becuase i also tought that it was the right way for it to be conceived

º.O

Cache size does matter - valuable real estate on the chip, and the big issues - latency, hence why L1 cache is smaller then L2, and L2 smaller then L3 - the more cache, the slower the access to specific addresses, and to flush etc - L1 cache is usually at least ~10x faster then L2.