AMD starting to rebound? (technically if not yet financially)

[Amiga500]

As far as the graphics division are concerned.


-> The catalyst 8.1 driver is out sooner than expected - I think this is the crossfire X driver that alot of hopes are pinned on.

-> The RV670 (3870x2) is coming out shortly (23rd of this month).

-> The engineering samples of RV770 are out and apparently working - there are rumours of a 50% speed bump over RV670.



With regards the CPU crew:

-> There were rumours the B3 step did not fix the TLB errata, apparently these are incorrect. B3 works fine. The next stepping for Phenom/Barcelona is on 45nm.

-> IIRC the 45nm Barcelona gets a L3 cache jump from 2MB to 6MB - that will surely make a strong impact on the performance of the CPU.




Leaving the Barcelona/Phenom problems aside for a moment, AMD have executed R680 well, RV670 looks like it will come when the roadmap said too. RV770 is early if anything. The GPU section seem to be hitting their deadlines now (which wasn't always the case for ATI). If AMD can make the jump to 45nm Q3 this year, adding some incremental improvements to the Barcelona IPC, they will be in decent shape till Intel bring out Nehalem...

The questions are then, when is it due, and can Intel hit that deadline?

 

[LukeBird]

You'd certainly like to think so woudn't you!
I have to say, I've been thinking the same recently. ATi certainly seem to be on the warpath with the 3870X2 and the 3850 & 3870 certainly seem to offer mega performance for the £/$.
If AMD can smoothly (and quickly, as you said, Q3 is really where it has to be) get Phenom to 45nm then they are looking good.
Personally I think Intel will have problems with Nehalem, it's a completely new CPU to them, and I think they'll go through some pretty big teething problems with the IMC (that AMD has been through) and I reckon that'll delay it.
Intel will for sure have 45nm nailed by then, but AMD will be vice versa and have IMC & L3 nailed by then.
Certainly be interesting to see where things go, although I think some of the 'announcements' have been a little over the top!
Personally, I think 45nm was way over-hyped. It really doesn't seem to make that much difference compared to G0 65nm Intel's...

 

[Amiga500]

Personally, I think 45nm was way over-hyped. It really doesn't seem to make that much difference compared to G0 65nm Intel's...

I reckon we could see higher clocked Intels on 45nm if they (Intel) wanted to.


But, 65nm for AMD has been bad from the word go - none of the Brisbanes have achieved the same clock speeds as the earlier Windsor cores - and the Barcelona cores aren't exactly operating in a brilliant thermal envelope.

 

[epsilon84]

45nm by Q3 08? I guess I'll believe it when I see it... AMD tends to be operating on their own customized calendars these days.

 

[spoonboy]

Think your right about Nehalem, good chance it will be delayed. If their having problems shrinking mainstream quad cores to 45nm:

http://www.dailytech.com/Intel+Explains+45nm+Delays+Errata/article10362.htm

Then delays getting Nehalem ready are not unlikely. This reminds me of 'super jumbo' vs. 'dream liner'. Boeing thought it would have dreamliner out double quick while the world pointed at the a380 saying it was bound up in technical difficulties, fat, late and failing. In the end both ended up being delayed.

I just see a potential parallel thats all. Grand projects tend to face problems sooner or later.

 

[Xajel]

AMD have diffeculties with mastering 65nm from A64X2 them self, just look at the higher end X2's now; and ask your self a question, souldn't I see more 65nm in the high end ?

while AMD didn't Master 65nm yet, they are forced to build Phenoms wich is new and still have a long way of tweaks in order to have the all good things of it.. as Phenom is big ( yeh native QC = big silicon die ) and to be able to stay in the same TDP of high-end X2's Phenoms can be done with 90nm wich AMD already mastered very well, so they used 65nm...

so )1) they still didn't master 65nm. )2) Phenom die design still need a lot of tweaks in order to have it's full power...

I think after all this time with 65nm in AMD, and all products that came with 65nm, I think AMD has problems with 65nm not just design, but the technology it self is not mature yet by the way AMD is using it or at least AMD is forced to use it...
that's why AMD has very big hope of 45nm to help Phenom be a very clean and give it much accurate shot in clock vs. power arena

 

[Reynod]

Gee ... even tho I am an AMD fanboi I am not talking up stuff anymore and getting disappointed again.

When they deliver my faith will be restored.

Till then I'll hope in silence.

Even with an 8Mb cache Phenom / Barcelona will still have boring single socket IPC ... cache won't solve anything by simply bolting it on.

Speeding up the cache / IMC will.
Addressing the prefetch logic issues will.
A respin and increase in frequency will ... but your talking over 3Ghz performance at least.

 

[spoonboy]

"cache won't solve anything by simply bolting it on."

intel might disagree, seeing as they decided increasing it by 50% for the 45nm chips.

Intel quad cores have 8mb cache, phenoms have 2mb. Does that not suggest something to do with performance? hello, anybody in there?

 

[chunkymonster]

Even with an 8Mb cache Phenom / Barcelona will still have boring single socket IPC ... cache won't solve anything by simply bolting it on.

"...boring single socket Instructions Per Cycle..."?!?!? What the heck does that mean? As opposed to all the other boring single socket processors?

Intel has proven that increased cache size does improve performance, please refer to this THG article. It is reasonable to think that Phenom's L3 cache will be improved with an increase in speed as well as size. The Phenom IMC runs at core speed.

 

[LukeBird]

I reckon we could see higher clocked Intels on 45nm if they (Intel) wanted to.


But, 65nm for AMD has been bad from the word go - none of the Brisbanes have achieved the same clock speeds as the earlier Windsor cores - and the Barcelona cores aren't exactly operating in a brilliant thermal envelope.

I didn't mean clockspeed, I meant all the claims about running much cooler, less power etc.
It has obviously been lower than the 65nm cores, but not by the amount that was claimed.
Hopefully AMD will be able to pull themselves together and get 45nm Phenom's in '08.

 

[Reynod]

My point is that adding cache to a cpu that doesn't process the same Instructions Per Clock (as core2) won't help ... particularly when the cache is running slower than the core.

I suggest you do more reading and less "hello anybody there" or "What the heck does that mean".

The core2 cpu's benefit from the additional cache because they are fully utilising it ... AMD is not.

AMD's current 1.8Ghz L3 is inferior to a cache system that runs at core speed.

Look at the dreadful cache latencies for instance.

Your embarrassing the other AMD fanbois ... me for one.

Catch up ... I'm not on the blue team.

 

[rodney_ws]

Personally, I think 45nm was way over-hyped. It really doesn't seem to make that much difference compared to G0 65nm Intel's...

Ha! Tell that to the accountants at Intel.

 

[BSMonitor]

I didn't mean clockspeed, I meant all the claims about running much cooler, less power etc.
It has obviously been lower than the 65nm cores, but not by the amount that was claimed.
Hopefully AMD will be able to pull themselves together and get 45nm Phenom's in '08.

Talking completely out of ones arse.....

What data do you have to support this? What was claimed?

What makes anyone believe that AMD will pull a miracle stepping out of 45nm? They can't make a good 65nm processor, but 45nm... No problem?!?

 

[spuddyt]

i sure hope so.....

(btw, im surprised thunderman isn't here yet )

 

[keithlm]

The core2 cpu's benefit from the additional cache because they are fully utilising it ... AMD is not.

AMD's current 1.8Ghz L3 is inferior to a cache system that runs at core speed.

Your first comment quoted above is one way of looking at the half empty/half full glass.

The other way is to consider that Intel might have a design flaw and throwing more cache at it will work at speeding things up. This conclusion can be reached because an efficient design would have reached a point of diminishing returns probably somewhere between 256k-512k. Since we are not seeing any diminishing return on their cache size... then we must consider something awry with their cache that they can cash in on.

(Although perhaps they DID find the point of diminishing returns... but maybe they are no longer using L2 as cache system... but as an expensive alternative to main memory storage. If this is what they are doing then you must ask... isn't that okay since they actually produce better benchmarks? But at what cost? Won't multi-tasking and task-switching have a penalty that at some point in time that rears it's ugly head? Or to add another cliche... you can sweep it under the rug and ignore it for now; later somebody will notice it.)

EDIT: A benchmark that could turn off or bypass the cache would be very revealing. It would be good to see the details about the base system without the cache. (Sure it would be unrealistic in real world usage... but most benchmarks are not real world anyway.)


Concerning the second comment quoted above: many also believe you are correct in that the L3 cache should be at core speed.

 

[ryman554]

The other way is to consider that Intel might have a design flaw and throwing more cache at it will work at speeding things up. This conclusion can be reached because an efficient design would have reached a point of diminishing returns probably somewhere between 256k-512k. Since we are not seeing any diminishing return on their cache size... then we must consider something awry with their cache that they can cash in on.

Why do you say this?

It would seem that the lack of software optimization across cache lines means that there are more cache misses which means that you have to flush the cache more often.. even if I have the most advanced hardware cache predictor, where does that help me from the non-optimized software that's out there now?

The reason intel has a huge cache is that they pay a much larger penalty in clock-cycles for cache misses than AMD due to the FSB vs. IMC differences. That's all. That's also why AMD gets away with relatively little cache. (that and their forced to wrt their transistor budget)

 

[ryman554]

Personally, I think 45nm was way over-hyped. It really doesn't seem to make that much difference compared to G0 65nm Intel's...

Overhyped how?

Raw performance? Check out the overclocking abilities of the 45nm. Intel is wwaaayyyyy below the maximum they can get out of 45nm.

Power usage? Check out Anand and the 45nm power consumption ratings. Especially at load. It's night and day.

If you're arguing about the Penryn vs. Conroe... these two *aren't* supposed to be all that different. That's the thing about tick/tock. The tick copies the last tock on the previous generation... so performance is expected to be similar. It's the tock that will really show the power of the new process. Wait till Nehalem.

 

[someguy7]

design flaw and throwing more cache at it will work at speeding things up?

Sure adding more cache is going to speed things up but its not a design flaw. They are adding more cache cause they can + it increases peformance a little.

If you think intels current chips have a cache desing flaw just look at the 1mb e2 series. Of course the models with more cache perform a little better when clocked to the same speed.

But that isnt a design flaw. It shows that the design works. It works well with 1mb of cache and the more cache you add the faster the cpu gets. So when they do die shrinks they are going to add more cache to increase performance another a couple of percent.

 

[wingless]

Gee ... even tho I am an AMD fanboi I am not talking up stuff anymore and getting disappointed again.

When they deliver my faith will be restored.

Till then I'll hope in silence.

Even with an 8Mb cache Phenom / Barcelona will still have boring single socket IPC ... cache won't solve anything by simply bolting it on.

Speeding up the cache / IMC will.
Addressing the prefetch logic issues will.
A respin and increase in frequency will ... but your talking over 3Ghz performance at least.

I agree with you. Adding more cache won't do much for the Phenom but speeding it up will. It doesn't matter how fast the cores on the Phenom are if the cache which it uses to communicate between cores and to the system is running at 2.0Ghz. The Phenom is incredibly bottlenecked by this L3 and it's speed should be increased above all else.If you remember the mid 1990's when socket 7's had slow L3 cache. It helped a little but sometimes slowed the system down and was ultimately eliminated. On die cache speed should always be equal to core frequency IMO regardless of the level. Unlike Intel's FSB, Hyper Transport eliminates the need for the huge caches that Intel requires. You'll see this holds true when Nehalem comes out with their HT copy and won't need 6mb caches to get the same performance.

 

[TechnologyCoordinator]

With regards the CPU crew:

-> There were rumours the B3 step did not fix the TLB errata, apparently these are incorrect. B3 works fine. The next stepping for Phenom/Barcelona is on 45nm.

-> IIRC the 45nm Barcelona gets a L3 cache jump from 2MB to 6MB - that will surely make a strong impact on the performance of the CPU.

Links? Proof?

 

[keithlm]

But that isnt a design flaw. It shows that the design works. It works well with 1mb of cache and the more cache you add the faster the cpu gets. So when they do die shrinks they are going to add more cache to increase performance another a couple of percent.

So if I understand you... you are claiming that if they keep adding cache and it keeps adding speed... showing that their cache mechanism isn't really working like a cache... it is not a design flaw but a design goal.

I must surmise that people don't care about any penalty they may pay to get more speed by using a possibly faulty cache system. It seems some people think it is just better to focus on any gain and ignore any consequences.

I personally think it is a bad idea and it will end up coming back to bite them. Perhaps they should redesign their architecture; they can continue adding cache to milk their current architecture until the new one is available.

But then what do I know about anything? I do happen to remember that I was running a dual CPU system almost 8 years ago and everyone told me there was absolutely no advantage of any kind for doing this on a desktop system. They also told me that a single CPU system with a faster CPU would run benchmarks better. Back then both viewpoints were "correct". Which one was "better"?

EDIT: BTW -- I bring up my old dual cpu system because I saw the exact same arguments back then. "My single faster CPU benchmarks better than your dual CPU system. So mine is better." Nothing I could say would convince them that there were advantages beyond the (then existing) benchmarks. Flash forward: It's the SAME CONVERSATION now.

 

[spoonboy]

Links? Proof?

No i can vouch for this, this was on an earlier thread. I posted some links about this, think it was fudzilla or someone. Not the best source but often one of the very very few. Think the thread was 'b3 going swimmingly' or something.

 

[spoonboy]

As far as the graphics division are concerned.


-> The catalyst 8.1 driver is out sooner than expected - I think this is the crossfire X driver that alot of hopes are pinned on.

-> The RV670 (3870x2) is coming out shortly (23rd of this month).

-> The engineering samples of RV770 are out and apparently working - there are rumours of a 50% speed bump over RV670.



With regards the CPU crew:

-> There were rumours the B3 step did not fix the TLB errata, apparently these are incorrect. B3 works fine. The next stepping for Phenom/Barcelona is on 45nm.

-> IIRC the 45nm Barcelona gets a L3 cache jump from 2MB to 6MB - that will surely make a strong impact on the performance of the CPU.




Leaving the Barcelona/Phenom problems aside for a moment, AMD have executed R680 well, RV670 looks like it will come when the roadmap said too. RV770 is early if anything. The GPU section seem to be hitting their deadlines now (which wasn't always the case for ATI). If AMD can make the jump to 45nm Q3 this year, adding some incremental improvements to the Barcelona IPC, they will be in decent shape till Intel bring out Nehalem...

The questions are then, when is it due, and can Intel hit that deadline?

Here are those links,

Thread: http://www.tomshardware.co.uk/forum/247685-10-phenom-swimmingly-apparently

Source: http://www.theinquirer.net/gb/inquirer/news/2008/01/11/barcelona-b3s-fine

 

[TechnologyCoordinator]

Thank you Spponboy.

 

[spoonboy]

no actually its theinquirer, even better lol