AMD starting to rebound? (technically if not yet financially)

As far as the graphics division are concerned.


-> The catalyst 8.1 driver is out sooner than expected - I think this is the crossfire X driver that alot of hopes are pinned on.

-> The RV670 (3870x2) is coming out shortly (23rd of this month).

-> The engineering samples of RV770 are out and apparently working - there are rumours of a 50% speed bump over RV670.



With regards the CPU crew:

-> There were rumours the B3 step did not fix the TLB errata, apparently these are incorrect. B3 works fine. The next stepping for Phenom/Barcelona is on 45nm.

-> IIRC the 45nm Barcelona gets a L3 cache jump from 2MB to 6MB - that will surely make a strong impact on the performance of the CPU.




Leaving the Barcelona/Phenom problems aside for a moment, AMD have executed R680 well, RV670 looks like it will come when the roadmap said too. RV770 is early if anything. The GPU section seem to be hitting their deadlines now (which wasn't always the case for ATI). If AMD can make the jump to 45nm Q3 this year, adding some incremental improvements to the Barcelona IPC, they will be in decent shape till Intel bring out Nehalem...

The questions are then, when is it due, and can Intel hit that deadline?

I reckon we could see higher clocked Intels on 45nm if they (Intel) wanted to.


But, 65nm for AMD has been bad from the word go - none of the Brisbanes have achieved the same clock speeds as the earlier Windsor cores - and the Barcelona cores aren't exactly operating in a brilliant thermal envelope.

Think your right about Nehalem, good chance it will be delayed. If their having problems shrinking mainstream quad cores to 45nm:

http://www.dailytech.com/Intel+Exp [...] e10362.htm

Then delays getting Nehalem ready are not unlikely. This reminds me of 'super jumbo' vs. 'dream liner'. Boeing thought it would have dreamliner out double quick while the world pointed at the a380 saying it was bound up in technical difficulties, fat, late and failing. In the end both ended up being delayed.

I just see a potential parallel thats all. Grand projects tend to face problems sooner or later.

Gee ... even tho I am an AMD fanboi I am not talking up stuff anymore and getting disappointed again.

When they deliver my faith will be restored.

Till then I'll hope in silence.

Even with an 8Mb cache Phenom / Barcelona will still have boring single socket IPC ... cache won't solve anything by simply bolting it on.

Speeding up the cache / IMC will.
Addressing the prefetch logic issues will.
A respin and increase in frequency will ... but your talking over 3Ghz performance at least.

"...boring single socket Instructions Per Cycle..."?!?!? What the heck does that mean? As opposed to all the other boring single socket processors?

Intel has proven that increased cache size does improve performance, please refer to this THG article. It is reasonable to think that Phenom's L3 cache will be improved with an increase in speed as well as size. The Phenom IMC runs at core speed.

My point is that adding cache to a cpu that doesn't process the same Instructions Per Clock (as core2) won't help ... particularly when the cache is running slower than the core.

I suggest you do more reading and less "hello anybody there" or "What the heck does that mean".

The core2 cpu's benefit from the additional cache because they are fully utilising it ... AMD is not.

AMD's current 1.8Ghz L3 is inferior to a cache system that runs at core speed.

Look at the dreadful cache latencies for instance.

Your embarrassing the other AMD fanbois ... me for one.

Catch up ... I'm not on the blue team.

Talking completely out of ones arse.....

What data do you have to support this? What was claimed?

What makes anyone believe that AMD will pull a miracle stepping out of 45nm? They can't make a good 65nm processor, but 45nm... No problem?!?

Your first comment quoted above is one way of looking at the half empty/half full glass.

The other way is to consider that Intel might have a design flaw and throwing more cache at it will work at speeding things up. This conclusion can be reached because an efficient design would have reached a point of diminishing returns probably somewhere between 256k-512k. Since we are not seeing any diminishing return on their cache size... then we must consider something awry with their cache that they can cash in on.

(Although perhaps they DID find the point of diminishing returns... but maybe they are no longer using L2 as cache system... but as an expensive alternative to main memory storage. If this is what they are doing then you must ask... isn't that okay since they actually produce better benchmarks? But at what cost? Won't multi-tasking and task-switching have a penalty that at some point in time that rears it's ugly head? Or to add another cliche... you can sweep it under the rug and ignore it for now; later somebody will notice it.)

EDIT: A benchmark that could turn off or bypass the cache would be very revealing. It would be good to see the details about the base system without the cache. (Sure it would be unrealistic in real world usage... but most benchmarks are not real world anyway.)

Concerning the second comment quoted above: many also believe you are correct in that the L3 cache should be at core speed.

Overhyped how?

Raw performance? Check out the overclocking abilities of the 45nm. Intel is wwaaayyyyy below the maximum they can get out of 45nm.

Power usage? Check out Anand and the 45nm power consumption ratings. Especially at load. It's night and day.

If you're arguing about the Penryn vs. Conroe... these two *aren't* supposed to be all that different. That's the thing about tick/tock. The tick copies the last tock on the previous generation... so performance is expected to be similar. It's the tock that will really show the power of the new process. Wait till Nehalem.

I agree with you. Adding more cache won't do much for the Phenom but speeding it up will. It doesn't matter how fast the cores on the Phenom are if the cache which it uses to communicate between cores and to the system is running at 2.0Ghz. The Phenom is incredibly bottlenecked by this L3 and it's speed should be increased above all else.If you remember the mid 1990's when socket 7's had slow L3 cache. It helped a little but sometimes slowed the system down and was ultimately eliminated. On die cache speed should always be equal to core frequency IMO regardless of the level. Unlike Intel's FSB, Hyper Transport eliminates the need for the huge caches that Intel requires. You'll see this holds true when Nehalem comes out with their HT copy and won't need 6mb caches to get the same performance.

So if I understand you... you are claiming that if they keep adding cache and it keeps adding speed... showing that their cache mechanism isn't really working like a cache... it is not a design flaw but a design goal.

I must surmise that people don't care about any penalty they may pay to get more speed by using a possibly faulty cache system. It seems some people think it is just better to focus on any gain and ignore any consequences.

I personally think it is a bad idea and it will end up coming back to bite them. Perhaps they should redesign their architecture; they can continue adding cache to milk their current architecture until the new one is available.

But then what do I know about anything? I do happen to remember that I was running a dual CPU system almost 8 years ago and everyone told me there was absolutely no advantage of any kind for doing this on a desktop system. They also told me that a single CPU system with a faster CPU would run benchmarks better. Back then both viewpoints were "correct". Which one was "better"?

EDIT: BTW -- I bring up my old dual cpu system because I saw the exact same arguments back then. "My single faster CPU benchmarks better than your dual CPU system. So mine is better." Nothing I could say would convince them that there were advantages beyond the (then existing) benchmarks. Flash forward: It's the SAME CONVERSATION now.

Here are those links,

Thread: http://www.tomshardware.co.uk/foru [...] apparently

Source: http://www.theinquirer.net/gb/inqu [...] a-b3s-fine

no actually its theinquirer, even better lol

Absolutely correct......just like they got lots of new, profitable products on the market last year:
QFX...............Q107
Brisbane.........Q107
Barcelona.......Q307
Phenom..........Q407

I dont know if AMD can survive another year of 'new' products. Given their current success rate with 'new' products, I would think they need to concentrate on fixing their current products before contemplating more new stuff.

Rebound? or just ordinary operation that you think it is a rebound?

They should have the XFire driver ready much sooner than Jan08...
They should have fix the TLB errata problem before the release of
Phenom...
They should have something in middle class as 3850/3870 at the time
they released HD 2900...

I would say AMD is working hard on fix the problem in past that they
should have been fixed, in order not to be working badly financially and
being purchased by someone like NVIDIA or Motorola...

What should a rebound of AMD be like?
-> announce of R700 with the H1 of 2008
-> announce of K11 or something like that, at least with a detailed
scheduled date of release
-> announce of a confirmed release day of fusion platform before Q2 2009
-> more detail of future development of AMD, in whatever way

With what we see now, I just see that AMD is trying to stand up with
whatever it have on hand, well, very hardly...
A rebound? at least at the day AMD have any future plan which is
technically competitive...

They launched it, then put a stop ship on it to anyone but qualified customers. Qualifies as a launch AFAIC. The boat sailed....that it started sinking when came off the rails and hit the water is moot....it couldnt have started sinking if they didnt put it in the water.

Adding cache is not a design goal, but more like part of the FSB architecture. Intel needs to use larger cache to hide the latency and lower bandwidth offered by FSB. So far they're doing very good.

The new one is scheduled to come out in Q408. I would personally speculate it would be pushed back to Q109, but I'm sure ryman has more information regarding this matter.

Its the same conversation for some people, and a lot different for others. I'm not going to fork out 300 bucks to get a quad if all I do is surf and game. For me, the question is more of a "what good does it do for me" than "oh look I can extra 300 points on 3DMark". I'm sure this also applies to others.

Well, there were 2 reasons why NVIDIA pulled the trick:
- AMD were not even been able to push something which can out-perform 8800GTX (not to say Ultra),
NVIDIA no reason that push something to compet with itself...
- 1st generation DX10 card actually perform badly in DX10 game at the 17" LCD native resolution at the time.
NVIDIA had no reason to push out some sub-USD200 display card with bad performance at 1280 x 1024,
which the market would think the card should be able to handle, in order not to be blamed by the market...
(actually NVIDIA should be able to push something quickly if AMD were pushing it hardly with something like
HD 2700/2950, just an architecture/die shrink or another slower clock version which can be produced at low cost
and working with cheap heat-sink solution. They had done the trick at the time with FX5200/5600, which perform
badly on DirectX 9, with the same trick...they just don't have to at the time...)

I Agree 100%

AMD 45nm is out in 2009, not 2008 - this is straight from AMD's CTO.

He also said that AMD is on schedule to come out with its 45-nanometer manufacturing process in 2009 as well.

http://www.mercextra.com/blogs/tak [...] il-hester/[i][/i]

That's a link to a Phenom processor, not a Barcelona processor.

The 'launch' was last September and to this date you still can't buy a server with Barcelona processors in it from Dell, HP, Sun, IBM etc.