Hi everyone,
These days I've been reading A LOT about overclocking and other stuff, but I still have some questions I can´t solve either in books or on the net, please.
1) According to FSB/DRAM ratios, does the memory bus have a completely different clock from the FSB? Is it generated by another independent clock-generator circuit? (the cpu clock is FSB x multiplier, but the memory clock may not (e.g.6/5 ratio) )
2) RAM latencies are the number of clock cycles it takes to perform a certain memory operation. But...do those cycles refer to the FSB/memory clock(1:1)? I've read many times that "DDR transfers twice data in one cycle than the preceding SDR" . In fact, the "PC-x" nomenclature is found this way:
(memory bus clock rate) × 2 (for dual rate) × 8 bytes
But... where are the latencies here?? This formula supposes data (128 bits) is transferred in only one cycle!?? And consequently, all steps in a read/write process are performed with almost no timing signals! (only 1 rising edge and 1 falling edge)
3) In memory asynchronous mode, how the CPU know when to retrieve data? In synchronous mode (1:1 ratio) I suppose the CPU adds wait states (for that instruction) according to the memory clock frequency... but, again, here I suppose a write/read is performed within a single memory clock cycle, which may not be true.
4) Finally, the Pentium 4 has a QDR (x4) bus, but it still works with DDR (x2) memories. How come an external system can modify the way a DDR memory works in the same amount of time?
I think my questions are quite concise to be answered in a direct way. Help me please, Thanks a lot
These days I've been reading A LOT about overclocking and other stuff, but I still have some questions I can´t solve either in books or on the net, please.
1) According to FSB/DRAM ratios, does the memory bus have a completely different clock from the FSB? Is it generated by another independent clock-generator circuit? (the cpu clock is FSB x multiplier, but the memory clock may not (e.g.6/5 ratio) )
2) RAM latencies are the number of clock cycles it takes to perform a certain memory operation. But...do those cycles refer to the FSB/memory clock(1:1)? I've read many times that "DDR transfers twice data in one cycle than the preceding SDR" . In fact, the "PC-x" nomenclature is found this way:
(memory bus clock rate) × 2 (for dual rate) × 8 bytes
But... where are the latencies here?? This formula supposes data (128 bits) is transferred in only one cycle!?? And consequently, all steps in a read/write process are performed with almost no timing signals! (only 1 rising edge and 1 falling edge)
3) In memory asynchronous mode, how the CPU know when to retrieve data? In synchronous mode (1:1 ratio) I suppose the CPU adds wait states (for that instruction) according to the memory clock frequency... but, again, here I suppose a write/read is performed within a single memory clock cycle, which may not be true.
4) Finally, the Pentium 4 has a QDR (x4) bus, but it still works with DDR (x2) memories. How come an external system can modify the way a DDR memory works in the same amount of time?
I think my questions are quite concise to be answered in a direct way. Help me please, Thanks a lot